參數(shù)資料
型號(hào): ST52E430B/D
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝: WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù): 13/120頁(yè)
文件大?。?/td> 502K
代理商: ST52E430B/D
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ST52T430/E430
from 6 (fuzzy instructions) to 26 (DIVISION) clock
pulses to be performed.
The DPU receives, stores and sends the
instructions coming from the EPROM, the RAM or
from the peripherals in order to execute them.
2.1.1 Program Counter
The Program Counter (PC) is a 13-bit register that
contains the address of the next memory location
to be processed by the core. This memory location
may be an opcode, an operand or an address of an
operand.
The 13-bit length allows the direct addressing of
8162 bytes in the program space.
After having read the current instruction address,
the PC value is incremented. The result of this
operation is shifted back into the PC.
The PC can be changed in the following ways:
n
JP (Jump)
PC = Jump Address
n
Interrupt
PC = Interrupt Vector
n
RETI
PC = Pop (stack)
n
RET
PC = Pop (stack)
n
CALL
PC = Subroutines address
n
Reset
PC = Reset Vector
n
Normal Instruction PC = PC + 1
2.1.2 Flags
The ST52x430 core includes different set of flags
that correspond to 2 different modes: normal
mode and interrupt mode. Each set of flags consist
of a CARRY flag (C), a ZERO flag (Z) and SIGN flag
(S). One set (CN, ZN, SN) is used during normal
operation and one is used during the interrupt
mode (CI, ZI, SI). Formally the user has to
manage only a set of flag: C, Z and S.
The ST52x430 core uses the flags that correspond
to the actual mode: as soon as an interrupt is
generated, the ST52x430 core uses the interrupt
flags instead of the normal flags.
Each interrupt level has its own set of flags, that it is
saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically, when a RETI instruction is executed.
If the MCU was in the normal mode before an
interrupt, when the RETI instruction is executed,
the normal flags are restored.
Note: A CALL subroutine is a normal mode
execution. For this reason a RET instruction,
consequent to a CALL instruction, does not affect,
the normal mode set of flags.
The flags are not cleared during the context
switching and remain in the state they were at the
exit of the last interrupt routine switching.
ST52X430 CORE
PROGRAM MEMORY
RAM
CONTROL UNIT
DPU
ALU
ON CHIP PERIPHERALS
PERIPHERAL REGISTERS
CONFIGURATION
REGISTERS
INPUT REGISTERS
LDRI
LDCR
LDPR
LDRC
LDCE
PERIPHERAL
BLOCK
Figure 2.5 Address Spaces Description
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