參數(shù)資料
型號(hào)： ST52E430B/D
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 20 MHz, MICROCONTROLLER, CDIP32
封裝： WINDOWED, SHRINK, CERAMIC, DIP-32
文件頁(yè)數(shù)： 61/120頁(yè)
文件大?。?/td> 502K
代理商： ST52E430B/D
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ST52T430/E430
One Channel Continuous Mode
In this mode (SEQ = ‘0’’, LP = ‘1’) a continuous
conversion flow is entered by a start event on the
channel selected by the bit CH0, CH1, CH2.
i.e CH(2:0) = ‘011’ means continuous conversion
of channel 3. At the end of each conversion the
relative IR is updated with the last conversion
result, while the former value is lost.
To stop the conversion STR has to be set to ‘0’.
Multiple Channels Continuous Mode
In this mode (SEQ = ‘1’’, LP = ‘1’) a continuous
conversion flow is entered by a start event on the
channels selected by the bits CH0, CH1, CH2.
i.e CH(2:0) = ‘011’ means continuous conversion
of channel 0,1,2 and 3.
At the end of each conversion the relative IRs are
updated with the last conversion results, while the
former values are lost.
To stop the conversion STR has to be set to ‘0’.
7.2.2 Power down Mode
Before enabling any A/D operation mode, set the
POW bit of the A/D configuration register to ‘1’ at
least 60 ms before the first conversion starts to
enable the biasing circuit inside the analog section
of the converter. Clearing the POW bit (POW = ‘0’)
is useful when the A/D is not used so reducing the
total chip power consumption. This state is also
the reset configuration and it is forced by hardware
when the core is in HALT state (after a HALT
instruction execution).
7.3 A/D Registers Description
The result of the conversions of the 8 available
channels are loaded in the 8 Input Register from
the decimal address 1 to the decimal address 8.
(IR (1:8) see table 2.2)). Every IR(1:8) is reloaded
with a new value at the end of the conversion of the
correspondent analog input.
By using the assembler instruction:
LDRI RAM_Reg. IR_i
the value stored in the i-th IR is transferred on the
RAM location RAM_Reg.
The A/D configuration register is the REG_CONF
3. The figure 6.2 shows the structure of this
register. This register manages the A/D logic
operation. The A/D configuration register
(REG_CONF 3) is programmable as following:
b7-b5 = CH2, CH1, CH0: Last Conversion
Address. These 3 bits define the last analog input.
The first analog input is converted, then the
address is incremented for the successive
conversion, until the channel identified by
CH0-CH2 is converted. The (CH2, CH1, CH0) bits
define the group of channels to be scanned. When
setting CH2=0 CH1=0 CH0=0 only channel 0 is
converted.
b4 = SCK: Master clock divider. The ST52x430 is
able to work with a clock frequency up to 20 MHz.
The SCK must be set to ‘1’ when the ST52x430
clock is higher then 10 MHz. It is useful to set SCK
= ‘1’ also when the clock master is lower than 10
MHz and an high accuracy is required.
b3 = SEQ: Multiple/Single channel. When SEQ is
set to ‘0’ a the channel identified by CH(2:0) is
converted. If SEQ is set to ‘1’ the group of channels
identified by CH(2:0) are converted.
b2= POW: Power Up/ Power Down. A logical ‘1’
enables the A/D logic and analog circuitry.
A logical level ‘0’ disables all power consuming
logic, thus allowing a low power idle status.
b1 = LP:Continuous/Single. When this bit is set to
‘1’ (continuous mode), the first conversions
sequence are started by the STR bit then a
continuous conversion flow is processed.
When LP=’0’ (single mode) only one sequence of
conversions is started when STR is set.
Bit
Name
Value
Description
0
STR
0
Stop Conversion
1
Start Conversion
1LP
0
Single Conversion
1
Continuous Conversions
2POW
0
A/D OFF
1
A/D ON
3
SEQ
0
Single Channel Conv.
1
Multiple Channels Conv
4SCK
0
Clock not Divided
1
Clock Divided
5
CH(2:0)
000
Channel 0
001
Channel 1
010
Channel 2
6
011
Channel 3
100
Channel 4
7
101
Channel 5
110
Channel 6
111
Channel 7
Table 7.10 A/D Conf. Register (Reg_Conf 3)
相關(guān)PDF資料
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