參數(shù)資料
型號(hào)： SST89C58-33-I-TQJE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： LEAD FREE, TQFP-44
文件頁數(shù)： 32/52頁
文件大小： 967K
代理商： SST89C58-33-I-TQJE
38
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
TABLE
12-7: DC ELECTRICAL CHARACTERISTICS
Ta = -40°C TO +85°C, 12MHZ DEVICES; VDD = 3.0-3.6V; VSS = 0V
Symbol
Parameter
Test Conditions
Limits
Units
Min
Max
VIL
Input Low Voltage
2.7 < VDD < 3.3
-0.5
0.7
V
VIH
Input High Voltage (ports 0, 1, 2, 3)
2.7 < VDD < 3.3
0.2VDD + 0.9
VDD + 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
2.7 < VDD < 3.3
0.7VDD
VDD + 0.5
V
VOL
Output Low Voltage (Ports 1.5, 1.6, 1.7)
VDD = 2.7V
IOL = 16 mA
1.0
V
VOL
Output Low Voltage (Ports 1, 2, 3)1
VDD = 2.7V
IOL = 100 A2
0.3
V
IOL = 1.6 mA2
0.45
V
IOL = 3.5 mA2
1.0
V
VOL1
Output Low Voltage (Port 0, ALE, PSEN#)1,3
VDD = 2.7V
IOL = 200 A2
0.3
V
IOL = 3.2 mA2
0.45
V
VOH
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4
VDD = 2.7V
IOH = -10 A
VDD - 0.3
V
IOH = -30 A
VDD - 0.7
V
IOH = -60 A
VDD - 1.5
V
VOH1
Output High Voltage (Port 0 in External Bus Mode)4
VDD = 2.7V
IOH = -200 A
VDD - 0.3
V
IOH = -3.2 mA
VDD - 0.7
V
IIL
Logical 0 Input Current (Ports 1, 2, 3)
VIN = 0.4V
-1
-75
A
ITL
Logical 1-to-0 Transition Current (Ports 1, 2, 3)5
VIN = 2V
-650
A
ILI
Input Leakage Current (Port 0)
0.45 < VIN < VDD-0.3
±10
A
RRST
RST Pulldown Resistor
40
225
k
IDD
Power Supply Current6
In-Application Programming mode
70
mA
Active Mode
22
mA
Standby (Stop Clock) Mode
Ta = 0°C to +70°C
70
A
Ta = -40°C to +85°C
88
A
Power Down Mode
Minimum VDD = 2.7V
Ta = 0°C to +70°C
40
A
Ta = -40°C to +85°C
50
A
T12-7.6 1131
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15mA
Maximum IOL per 8-bit port:
26mA
Maximum IOL total for all outputs: 71mA
If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due
to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN# = 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 & 2 may cause the VOH, ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the
address bits are stabilizing.
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