參數(shù)資料
型號(hào)： SST89C58-33-I-TQJE
廠(chǎng)商： SILICON STORAGE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： LEAD FREE, TQFP-44
文件頁(yè)數(shù)： 22/52頁(yè)
文件大?。?/td> 967K
代理商： SST89C58-33-I-TQJE
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
29
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
8.0 SECURITY LOCK
The Security feature protects against software piracy and
prevents the contents of the flash from being read by unau-
thorized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory locations. There are two different
types of security locks in the SST89C54/58 security lock
system, hard lock and SoftLock. (See Figure 8-1 and Table
8.1 Hard Lock
When the hard lock is activated, the MOVC instructions
executed from unlocked or SoftLocked program address
space, are disabled from reading code bytes in hard locked
memory blocks (See Table 8-2). The hard lock can either
lock both flash memory blocks or just lock the upper flash
memory block (Block 1). All External Host and IAP com-
mands except for Chip-Erase are ignored by the hard
locked memory blocks.
8.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the soft locked memory block through in-
application programming mode under a predetermined
secure environment. For example, if the Block 1 (4KB)
memory is hard locked, and the Block 0 (16KB/32KB)
memory is soft locked, code residing in Block 1 can pro-
gram Block 0. The following IAP mode commands issued
through the command mailbox register, SFCM, executed
from a hard locked block can be operated on a soft locked
block: Block-Erase, Sector-Erase, Byte-Program, Burst-
Program and Byte-Verify.
In external host mode, SoftLock behaves the same as a
hard lock.
8.3 Security Lock Status
The three bits that indicate the SST89C54/58 security lock
status, SB1, SB2 and SB3, are located in SFST[7:5]. As
shown in Figure 8-1 and Table 8-1, the three security lock
bits control the lock status of the primary and secondary
blocks of memory. There are four distinct levels of security
lock status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the sec-
ond level, although, both blocks are now locked and cannot
be written, they are available for Read operation via Byte-
Verify. In the third level, three different options are available:
Block 1 hard lock / Block 0 SoftLock, SoftLock on both
blocks, and hard lock on both blocks. Locking both blocks is
the same as Level 2 except Read operation isn’t available.
The fourth level of security is the most secure level. It
doesn’t allow read/write of internal memory or boot from
external memory. Please note that for unused combina-
tions of the security lock bit the chip will default to Level 4
status.
For details on how to program the security lock bits, refer to
the External Host Programming Mode (Section 4.1) and in-
application programming mode (Section 4.2).
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