參數(shù)資料
型號(hào)： SST89C58-33-I-TQJE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝： LEAD FREE, TQFP-44
文件頁(yè)數(shù)： 21/52頁(yè)
文件大?。?/td> 967K
代理商： SST89C58-33-I-TQJE
28
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
6.0 SERIAL I/O
The SST89C54/58 serial I/O port is a full-duplex UART
(Universal Asynchronous Receiver/Transmitter) that allows
data to be transmitted and received simultaneously in hard-
ware by the transmit and receive registers, respectively. The
serial I/O port performs the function of an UART. The trans-
mit and receive registers are both located in the Serial Data
Buffer (SBUF) special function register. Writing to the SBUF
register loads the transmit register, and reading from the
SBUF register obtains the contents of the receive register.
The serial I/O port has four modes of operation which are
selected by the Serial Port mode Specifier (SM0 and SM1)
bits of the Serial Port Control (SCON) special function reg-
ister. In all four modes, transmission is initiated by any
instruction that uses the SBUF register as a destination
register. Reception is initiated in Mode 0 when the Receive
Interrupt (RI) flag bit of the Serial Port Control (SCON) spe-
cial function register is cleared and the Reception Enable/
Disable (REN) bit of the SCON register is set. Reception is
initiated in other modes by the incoming start bit if the REN
bit of the SCON register is set.
7.0 WATCHDOG TIMER
The SST89C54/58 offer a hardware programmable Watch-
dog Timer (WDT) for fail safe operation against software
hang-up and automatic reset recovery.
To protect the system against software hang-up, the soft-
ware has to refresh the WDT within a user defined time
period. If the software fails to do this periodic refresh, an
internal hardware reset will be initiated if enabled
(WDRE=1). The software can be designed such that the
WDT times out if the program does not work properly. It
also times out if a software error is based on hardware
related problems.
The WDT in the SST89C54/58 share the same time base
with the flash controller unit. When the flash controller unit
is operating, the time base will be re-started by the hard-
ware periodically, therefore delaying the time-out period of
the watchdog timer. The upper 8-bits of the time base reg-
ister are used as the reload register of the WDT.
The internal oscillator that drives the WDT operates within
a frequency range as shown in Table 12-1. Minimum clock
cycle for the WDT is 7.7ms, typical 10ms.
Figure 7-1 provides a block diagram of the WDT. Two SFRs
(WDTC and WDTD) control watchdog timer operation.
Note:
WDTD won’t be effective until bit WDT is set.
A WDTD register can not be set to 0FFH.
WDT time-out period = (255-WDTD) x 7.7ms
(min.)
FIGURE
7-1: BLOCK DIAGRAM OF PROGRAMMABLE WATCHDOG TIMER
1131 F16.0
WDT Upper Byte
WDT Reset
Internal Reset
7.7 ms
min.
Counter
CLK
Ext. RST
WDTC
WDTD
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