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參數(shù)資料
| 型號： | SST89C58-33-I-TQJE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 967K |
| 代理商： | SST89C58-33-I-TQJE |
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Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
19
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
4.0 FLASH MEMORY PROGRAMMING
The SST89C54/58 internal flash memory can be pro-
grammed or erased using the following two methods:
External host mode
In-Application Programming (IAP) mode
4.1 External Host Programming Mode
External Host Programming mode allows the user to pro-
gram the Flash memory directly without using the CPU.
External host mode is entered by forcing PSEN# from a
logic high to a logic low while RST input is being held con-
tinuously high. The device will stay in external host mode
as long as RST = “1” and PSEN# = “0”.
A Read-ID operation is necessary to “arm” the device, no
other external host mode command can be enabled until a
Read-ID is performed. In external host mode, the internal
Flash memory blocks are accessed through the re-
assigned I/O port pins (see Figure 4-1 for details) by an
external host, such as an MCU programmer, PCB tester or
a PC controlled development board.
When the chip is in the external host mode, Port 0 pins are
assigned to be the parallel data input and output pins. Port
1 pins are assigned to be the non-multiplexed low order
address bus signals for the internal flash memory (A7-A0).
The first six bits of Port 2 pins (P2[5:0]) are assigned to be
the non-multiplexed upper order address bus signals for
the internal flash memory (A13-A8) along with two of the
Port 3 pins (P3[5] as A15 and P3[4] as A14). Two upper
order Port 2 pins (P2[7] and P2[6]) and two upper order
Port 3 pins (P3[7] and P3[6]) along with RST, PSEN#, ALE/
PROG#, EA# pins are assigned as the control signal pins.
The Port 3 pin (P3[3]) is assigned to be the ready/busy sta-
tus signal, which can be used for handshaking with the
external host during a flash memory programming opera-
tion. The flash memory programming operation (Erase,
Program, Verify, etc.) is internally self-timed.
The insertion of an “arming” command prior to entering the
external host mode by utilizing the Read-ID operation pro-
vides additional protection for inadvertent writes to the
internal flash memory caused by a noisy or unstable sys-
tem environment during power-up or brown-out conditions.
The external host mode uses twelve (12) hardware com-
mands, which are decoded from the control signal pins, to
facilitate the internal flash memory erase, program and ver-
ify processes. The external host mode is enabled on the
falling edge of PSEN#. The external host mode commands
are enabled on the falling edge of ALE/PROG#. The list in
Table 4-1 outlines all the commands and the respective
control signal assignment.
TABLE
4-1: EXTERNAL HOST MODE COMMANDS
Operation
RST
PSEN#
ALE/
PROG#
EA#
P3[7]
P3[6]
P2[7]
P2[6]
P0[7:0]
P1[7:0]
P3[5:4]
P2[5:0]
Read-ID
VIH1
VIL
VIH
VIL
DO
AL
AH
Chip-Erase
VIH1
VIL
1
1. Symbol
signifies a negative pulse and the command is asserted during the low state of ALE/PROG# input.
All other combinations of the above input pins are invalid and may result in unexpected behaviors.
VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Logic High Level (RST); X = Don’t care; AL = Address low order byte; AH = Address
high order byte; DI = Data Input; DO = Data Output; A[15:12] = 0xxxb for Block 0 (SST89C58), A[15:12] = 00xxb for Block 0 (SST89C54),
and A[15:12] = “1111b” for Block 1.
VIH
VIL
VIH
XX
X
Block-Erase
VIH1
VIL
VIH
VIL
VIH
X
A[15:12]
Sector-Erase
VIH1
VIL
VIH
VIL
VIH
XAL
AH
Byte-Program
VIH1
VIL
VIH
VIL
DI
AL
AH
Burst-Program
VIH1
VIL
VIH
VIL
VIH
VIL
DI
AL
AH
Byte-Verify (Read)
VIH1
VIL
VIH
VIL
DO
AL
AH
Prog-SB1
VIH1
VIL
VIH
XX
X
Prog-SB2
VIH1
VIL
VIH
VIL
VIH
XX
X
Prog-SB3
VIH1
VIL
VIH
VIL
VIH
VIL
VIH
XX
X
Prog-RB0
VIH1
VIL
VIH
VIL
XX
X
Prog-RB1
VIH1
VIL
VIH
VIL
VIH
XX
X
T4-1.5 1131
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