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參數(shù)資料
| 型號： | SST89C58-33-I-TQJE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大小： | 967K |
| 代理商： | SST89C58-33-I-TQJE |
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Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
23
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
4.1.6 Instructions to Perform External Host Mode
Commands
To program data into the memory array, apply power sup-
ply voltage (VDD) to VDD and RST pins, and perform the fol-
lowing steps:
1. Maintain RST high and toggle PSEN# from logic
high to low, in sequence per the appropriate timing
diagram.
2. Raise EA# High (either VIH or VH).
3. Issue Read-ID command to enable the external
host mode.
4. Verify that the memory blocks or sectors for pro-
gramming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
5. Select the memory location using the address
lines (P1[7:0], P2[5:0], P3[5:4]).
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse width.
8. Wait for low to high transition on READY/BUSY#
(P3[3]).
9. Repeat steps 5 - 8 until programming is finished.
10. Verify the flash memory contents.
4.2 In-Application Programming Mode
The SST89C54/58 offers 20/36 KByte of in-application pro-
grammable flash memory. During in-application program-
ming, the CPU of the microcontroller enters IAP mode. The
two blocks of flash memory allows the CPU to concurrently
execute user code from one block, while the other is being
reprogrammed. The CPU may also fetch code from an
external memory while all internal flash is being repro-
grammed. The mailbox registers (SFST, SFCM, SFAL,
SFAH, SFDT and SFCF) located in the Special Function
Register (SFR), control and monitor the device’s erase and
program process.
Table 4-3 outlines the commands and their associated set-
tings of the mailbox registers.
4.2.1 In-Application Programming Mode Clock
Source
During IAP mode, both the CPU core and the flash control-
ler unit (FCU) are driven off the external clock. However, an
internal oscillator will provide timing references for Program
and Erase operations. The duration of Program and Erase
operations will be identical between external host mode
and In-Application mode. The internal oscillator is only
turned on when required, and is turned off as soon as the
Flash operation is complete.
4.2.2 IAP Enable Bit
The IAP enable bit, SFCF[6], initializes in-application pro-
gramming mode. Until this bit is set, all flash programming
IAP commands will be ignored.
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