參數(shù)資料
型號: SST89C58-33-I-TQJE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝: LEAD FREE, TQFP-44
文件頁數(shù): 26/52頁
文件大?。?/td> 967K
代理商: SST89C58-33-I-TQJE
32
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
9.0 RESET
A system reset initializes the MCU and begins program
execution at program memory location 0000H. The reset
input for the SST89C54/58 is the RST pin. In order to reset
the device, a logic level high must be applied to the RST pin
for at least two machine cycles (24 clocks), after the oscilla-
tor becomes stable. ALE and PSEN# are weakly pulled
high during reset. During reset, ALE and PSEN# output a
high level in order to perform correct reset. This level must
not be affected by external element. A system reset will not
affect the 256 Bytes of on-chip RAM while the SST89C54/
58 is running, however, the contents of the on-chip RAM
during power up are indeterminate. All Special Function
Registers (SFR) return to their reset values, which are out-
lined in Tables 3-3 to 3-7.
9.1 Power-On Reset
At initial power up, the port pins will be in a random state
until the oscillator has started and the internal reset algo-
rithm has weakly pulled all pins high. Powering up the
device without a valid reset could cause the CPU to
start executing instructions from an indeterminate
location. Such undefined states may inadvertently cor-
rupt the code in the flash.
When power is applied to the SST89C54/58, the RST pin
must be high long enough for the oscillator to start up (usu-
ally several milliseconds for a low frequency crystal), in
addition to two machine cycles for a valid Power-On Reset.
An example of a method to extend the RST signal is to
implement a RC circuit by connecting the RST pin to VDD
through a 10F capacitor and to VSS through an 8.2 KOhm
resistor as shown in Figure 10-1. Note that if an RC circuit
is being used, provisions should be made to ensure the
VDD rise time does not exceed 10 ms. The oscillator start-
up time depends on the crystal frequency.
For a low frequency oscillator with slow start-up time the
reset signal must be extended in order to account for the
slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming
at an indeterminate location, which may cause corruption
in the flash memory.
Crystal
Typical Start-up Time
10MHz
1ms
1MHz
10ms
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