- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98142 > SST89C58-33-I-TQJE (SILICON STORAGE TECHNOLOGY INC) 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | SST89C58-33-I-TQJE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 967K |
| 代理商： | SST89C58-33-I-TQJE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
22
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
4.1.4 External Host Mode Clock Source
In external host mode, an internal oscillator will provide
clocking for the SST89C54/58. The on-chip oscillator will
be turned on as the SST89C54/58 enters external host
mode; i.e. when PSEN# goes low while RST is high. The
oscillator provides both clocking for the flash control unit as
well as timing references for Program and Erase opera-
tions. During external host mode, the CPU core is held in
reset. Upon exit from external host mode, the internal oscil-
lator is turned off.
The same oscillator also provides the time base for the
watchdog timer and timing references for IAP mode Pro-
gram and Erase operations. See more detailed description
in later sections.
4.1.5 Flash Operation Status Detection Via
External Host Handshake
The SST89C54/58 provide two methods for an external
host to detect the completion of a flash memory operation
to optimize the Program or Erase time. The end of a flash
memory operation cycle can be detected by: 1) monitoring
the READY/BUSY# bit at P3[3]; 2) monitoring the Data#
Polling bit at P0[7] and P0[3].
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the READY/BUSY# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
flash control unit (FCU). P3[3] is driven high when the Flash
programming operation is completed to indicate the Ready
status.
During a Burst-Program operation, P3[3] is driven high
(Ready) in between each byte programmed among the
burst to indicate the ready status to receive the next byte.
When the external host detects the Ready status after a
byte among the burst is programmed, it should then put the
data/address (within the same row) of the next byte on the
bus and drive ALE/PROG# low (pulse), before the time-out
limit expires. See Table 12-11 for details. Burst-Program
command presented after time-out will wait until the next
cycle. Therefore, it will have longer programming time.
4.1.5.2 Data# Polling (P0[7] and P0[3])
During a Program operation, any attempts to read (Byte-
Verify), while the device is busy, will receive the comple-
ment of the data for the last byte loaded (logic low, i.e. “0”
for an erase) on P0[3] and P0[7] with the rest of the bits “0”.
During a Program operation, the Byte-Verify command will
read the data from the last byte loaded, not the data at the
address specified.
During a Burst-Program operation, the true data will be
read from P0[7], when the device completes each byte pro-
grammed among the burst to indicate the Ready status to
receive the next byte. When the external host detects the
Ready status after a byte among the burst is programmed,
it should then put the data/address (in the same row) of the
next byte on the bus and drive ALE/PROG# low immedi-
ately, before the time-out limit expires (See Table 12-11 for
details.). The true data will be read from P0[3], when the
Burst-Program command is terminated and the device is
ready for the next operation.
After security lock-bits are set:
If read on universal programmer, e.g. external host
mode, the programmer will read 00H instead of 0FFH.
If read by MOVC instruction, the programmer will
return 0FFH regardless of true data if MOVC is exe-
cuted in a block with lower level lock.
If read by the IAP Byte-Verify command, then SFDT
won’t update its data, i.e. SFDT will keep its OLD data
unchanged, so the user’s application code will get ran-
dom data based on the old SFDT value. This IAP
Byte-Verify command is executed in a block with lower
level lock.
The termination of the Burst-Program can be accom-
plished by: 1) Change to a new row address (Note: the
Address range is different for the 4Kx8 flash Block 1 and for
the 16/32K x 8 flash Block 0.); 2) Change to a new com-
mand that requires a high to low transition of the ALE/
PROG# (for example, any Erase or Program command, 3)
Wait for time out limit to expire (20 s) before programming
the next byte.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST89E516RD-40-C-QIF | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, QCC40 |
| SST89E516RD2-40-C-NJE | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| SST89E52RD-40-C-PI | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40 |
| SST89V58RD-33-C-PI | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40 |
| SST89V58RD-33-I-PIE | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST89C58RC-40-C-QIF | 功能描述:8位微控制器 -MCU 34K (32Kx8K) SM-Bus 40MHz 2.7-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89C58RC-40-C-QIF-T | 功能描述:8位微控制器 -MCU 4.5-5.5V FlashFlex 8b 8051 Microctrl RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89C58RC-40-I-NJE | 制造商:Microchip Technology Inc 功能描述:8 BIT MICROCONTROLLER WITH 40K - Rail/Tube 制造商:Microchip Technology Inc 功能描述:Microchip SST89C58RC-40-I-NJE Microcontrollers (MCU) |
| SST89C58RC-40-I-QIF | 功能描述:8位微控制器 -MCU 40K (32Kx8K) SM-Bus 40MHz 2.7-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SST89C58RC-40-I-TQJE | 功能描述:8位微控制器 -MCU 40K (32Kx8K) SM-Bus 40MHz 2.7-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。