參數(shù)資料
型號: SST89C58-33-I-TQJE
廠商: SILICON STORAGE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44
封裝: LEAD FREE, TQFP-44
文件頁數(shù): 27/52頁
文件大?。?/td> 967K
代理商: SST89C58-33-I-TQJE
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
33
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
10.0 POWER-SAVING MODES
The SST89C54/58 provides power saving modes of opera-
tion for applications where power consumption is critical.
The two power saving modes are: Power Down and
Standby (Stop Clock).
10.1 Power Down Mode
The Power Down mode is entered by setting the PD bit in
the PCON register. In Power Down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupt only.
The SST89C54/58 exits Power Down mode through either
an enabled external level sensitive interrupt INTx or a hard-
ware reset. The interrupt clears the PD bit, the oscillator
restarts and stabilizes, then the program resumes execu-
tion beginning at the instruction immediately following the
one which invoked the Power Down mode. The hardware
reset redefines all the SFRs but does not change the on-
chip RAM.
10.2 Standby Mode (Stop Clock)
Standby mode is similar to Power Down mode, except that
Power Down mode is initiated by a software command and
Standby mode is initiated by external hardware gating off
the external clock to the SST89C54/58. The on-chip RAM
and SFR data are maintained in the Standby mode. The
device resumes operation at the next instruction when the
clock is reapplied to the part.
Table 10-1 outlines the two power-saving modes, including
entry and exit procedures and MCU functionality.
FIGURE
10-1: POWER-ON RESET CIRCUIT
1131 F18.0
VDD
10F
+
-
8.2K
SST89C54/58
RST
XTAL2
XTAL1
12MHz
C1
C2
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