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| 型號(hào)： | SST89C58-33-I-TQJE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | LEAD FREE, TQFP-44 |
| 文件頁(yè)數(shù)： | 28/52頁(yè) |
| 文件大?。?/td> | 967K |
| 代理商： | SST89C58-33-I-TQJE |
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34
Data Sheet
FlashFlex51 MCU
SST89C54 / SST89C58
2004 Silicon Storage Technology, Inc.
S71131-04-000
6/04
11.0 CLOCK INPUT OPTIONS
Shown in Figure 11-1 are the input and output of an inter-
nal inverting amplifier (XTAL1, XTAL2), which can be con-
figured for use as an on-chip oscillator.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
At start-up, the external crystal oscillator may encounter a
higher capacitive load at XTAL1 due to interaction between
the amplifier and its feedback capacitance. However, the
capacitance will not exceed 15pF once the external signal
meets the VIL and VIH specifications.
11.1 Recommended Capacitor Values for
Crystal Oscillator
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one applica-
tion to another. C1 and C2 capacitors should be adjusted
appropriately for each design. Table 11-1 below, shows the
typical values for C1 and C2 by crystal type.
TABLE
10-1: SST89C54/58 POWER SAVING MODES
Mode
Initiated by
Current Drain
State of MCU
Exited by
Power Down Mode
Software
(Set PD bit in PCON)
MOV PCON, #02H
Typically 15-20 A. Min-
imum VDD for Power
Down mode is 2.7V.
CLK is stopped. On-
chip SRAM and SFR
data will be main-
tained. ALE and
PSEN# signals at a
LOW level during
Power Down. External
Interrupts are only
active for level sensi-
tive interrupts, if
enabled.
Enabled external level
sensitive interrupt INTx
or hardware reset. Start
of interrupt clears PD
bit and exits Power
Down mode, after the
ISR RETI instruction
program resumes exe-
cution beginning at the
instruction following the
one that invoked Power
Down mode. A user
could consider placing
two or three NOP
instructions after the
instruction that invokes
Power Down mode to
eliminate any problems,
or by hardware reset.
Standby (Stop Clock)
Mode
External hardware
gates turn off the exter-
nal clock input to the
MCU. This gating
should be synchro-
nized with an input
clock transition (low-to-
high or high-to-low).
Typically 15-20 A. Min-
imum VDD for Standby
mode is 2.7V.
CLK is frozen. On-chip
RAM and SFR data is
maintained. ALE and
PSEN# are maintained
at the levels prior to the
clock being frozen.
Gate ON external clock.
Program execution
resumes at the instruc-
tion following the one
during which the clock
was gated off.
T10-1.5 1131
TABLE
11-1: RECOMMENDED VALUES FOR C1 AND
C2 BY CRYSTAL TYPE
Crystal
C1 = C2
Quartz
20-30pF
Ceramic
40-50pF
T11-1.1 1131
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