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| 型號： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 64/182頁 |
| 文件大?。?/td> | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
9-9
1997-08-01
Power Saving Modes
C515A
9.6
Hardware Power Down Mode
The power down mode of the C515A can also be initiated by an external signal at the pin HWPD.
Because this power down mode is activated by an external hardware signal it mode is referred to
as hardware power down mode in opposite to the program controlled software power down mode.
Pin PE/SWD has no control function for the hardware power down mode; it enables and disables
only the use of all software controlled power saving modes (idle mode, software power down mode).
The function of the hardware power down mode is as follows:
– The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the hardware
power down mode; as mentioned above this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete internal
reset sequence. This takes two machine cycles; all pins have their default reset states during this
time. This reset has exactly the same effects as a hardware reset; i.e.especially the watchdog timer
is stopped and its status flag WDTS is cleared. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled, the on-chip
oscillator as well as the oscillator watchdog's RC oscillator. At the same time the port pins and
several control lines enter a floating state as shown in table 9-2. In this state the power consumption
is reduced to the power down current
I
PD . Also the supply voltage can be reduced.
Table 9-2 also lists the voltages which may be applied at the pins during hardware power down
mode without affecting the low power consumption.
Table 9-2
Status of all Pins During Hardware Power Down Mode
Pins
Status
Voltage Range at Pin During
HW-Power Down
P0, P1, P2, P3, P4, P5
Floating outputs/
Disabled input function
V
SS ≤ VIN ≤ VCC
EA
Active input
V
IN = VCC or VIN = VSS
PE/SWD
Active input, Pull-up resistor
Disabled during HW power down
V
IN = VCC or VIN = VSS
XTAL 1
Active output
pin may not be driven
XTAL 2
Disabled input function
V
SS ≤ VIN ≤ VCC
PSEN, ALE
Floating outputs/
Disabled input function
(for test modes only)
V
SS ≤ VIN ≤ VCC
RESET
Active input; must be at high level if
HWPD is used
V
IN = VCC
V
ARef
ADC reference supply input
V
SS ≤ VIN ≤ VCC
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