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參數(shù)資料
| 型號(hào)： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 123/182頁(yè) |
| 文件大?。?/td> | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
5-3
1997-08-01
Reset / System Clock
C515A
5.2
Fast Internal Reset after Power-On
The C515A uses the oscillator watchdog unit for a fast internal reset procedure after power-on.
Figure 5-1 shows the power-on sequence under control of the oscillator watchdog.
Normally the devices of the 8051 family do not enter their default reset states before the on-chip
oscillator starts. The reason is that the external reset signal must be internally synchronized and
processed in order to bring the device into the correct reset state. Especially if a crystal is used the
start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an
undefined state which could have severe effects especially to actuators connected to port pins.
In the C515A the oscillator watchdog unit avoids this situation. In this case, after power-on the
oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2
microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip
oscillator because this has not yet started (a failure is always recognized if the watchdog's RC
oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog
uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output.
This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-7).
Under worst case conditions (fast
V
CC rise time - e.g. 1s, measured from VCC = 4.25 V up to stable
port condition), the delay between power-on and the correct port reset state is :
– Typ.:
18
s
– Max.:
34
s
The RC oscillator will already run at a
V
CC below 4.25V (lower specification limit). Therefore, at
slower
V
CC rise times the delay time will be less than the two values given above.
After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function;
then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator
clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-7, II).
Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset
request is released (figure 5-7, III). However, an externally applied reset still remains active (figure
5-7, IV) and the device does not start program execution (figure 5-7, V) before the external reset is
also released.
Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply
the external reset signal when powering up. The reasons are as follows:
–
Termination of software power down mode
–
Reset of the status flag OWDS that is set by the oscillator watchdog during the power up
sequence.
Using a crystal or ceramic resonator for clock generation, the external reset signal must be held
active at least until the on-chip oscillator has started and the internal watchdog reset phase is
completed (after phase III in figure 5-7). When an external clock generator is used, phase II is very
short. Therefore, an external reset time of typically 1 ms is sufficent in most applications.
Generally, for reset time generation at power-on an external capacitor can be applied to the RESET
pin.
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