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參數(shù)資料
| 型號： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 26/182頁 |
| 文件大?。?/td> | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
6-70
1997-08-01
On-Chip Peripheral Components
C515A
6.4.5
A/D Converter Calibration
The C515A A/D converter includes hidden internal calibration mechanisms which assure a save
functionality of the A/D converter according to the DC characteristics. The A/D converter calibration
is implemented in a way that a user program which executes A/D conversions is not affected by its
operation. Further, the user program has no control on the calibration mechanism. The calibration
itself executes two basic functions :
– Offset calibration
: compensation of the offset error of the internal comparator and
capacitor network
– Linearity calibration
: correction of the binary weighted capacitor network
The A/D converter calibration operates in two phases : calibration after a reset operation and
calibration at each A/D conversion. The calibration phases are controlled by a state machine in the
A/D converter. This state machine once executes a reset calibration phase after each reset
operation of the C515A and stores the result values of the reset calibration phase after its end in an
internal RAM. Further, these values are updated after each A/D conversion.
After a reset operation the A/D calibration is automatically started. This reset calibration phase
which takes 3328 fADC clocks, alternating offset and linearity calibration is executed. Therefore, at
12 MHz oscillator frequency and with the default prescaler value of 4, a reset calibration time of
approx. 2.2 ms is reached. The reset calibration phase is defined as follows (tOSC = 1 / fOSC) :
– Prescaler 4 selected : Reset calibration phase = 3328 x fADC = 13312 x tIN = 26624 x tOSC
– Prescaler 8 selected : Reset calibration phase = 3328 x fADC = 26624 x tIN = 53248 x tOSC
For achieving a proper reset calibration, the fADC prescaler value must satisfy the condition fADC
max ≤ 2 MHz. For oscillator frequencies above 16 MHz this condition is not met with the default
prescaler value (
÷4) after reset. Therefore, the prescaler of the A/D converter must be adjusted by
software immediately after reset by setting bit ADCL in SFR ADCON1. When setting bit ADCL
directly after reset as required for oscillator clocks greater or equal 16 MHz, the clock prescaler
ratio
÷8 is selected and therefore the absolute value for the reset calibration phase will be extended
by factor 2.
After a reset operation of the C515A, this means when a reset calibration phase is started, the total
unadjusted error TUE of the A/D converter is
± 6 LSB. After the reset calibration phase the A/D
converter is calibrated according to its DC characteristics (TUE =
± 2 LSB). Nevertheless, during
the reset calibration phase single or continuous A/D can be executed. In this case it must be
regarded that the reset calibration is interrupted and continued after the end of the A/D conversion.
Therefore, interrupting the reset calibration phase by A/D conversions extends the total reset
calibration time. If the specified total unadjusted error (TUE) has to be valid for an A/D conversion,
it is recommended to start the first A/D conversions after reset when the reset calibration phase is
finished.
After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled
to each A/D conversion. With this second calibration mechanism alternatively offset and linearity
calibration values, stored in the calibration RAM, are always checked when an A/D conversion is
executed and corrected if required.
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