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| 型號： | SAH-C515A-4R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | METRIC, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 170/182頁 |
| 文件大小： | 1917K |
| 代理商： | SAH-C515A-4R |
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Semiconductor Group
6-37
1997-08-01
On-Chip Peripheral Components
C515A
6.2.2.4
Using Interrupts in Combination with the Compare Function
The compare service of registers CRC, CC1, CC2 and CC3 is assigned to alternate output functions
at port pins P1.0 to P1.3. Another option of these pins is that they can be used as external interrupt
inputs. However, when using the port lines as compare outputs then the input line from the port pin
to the interrupt system is disconnected (but the pin’s level can still be read under software control).
Thus, a change of the pin’s level will not cause a setting of the corresponding interrupt flag. In this
case, the interrupt input is directly connected to the (internal) compare signal thus providing a
compare interrupt.
The compare interrupt can be used very effectively to change the contents of the compare registers
or to determine the level of the port outputs for the next “compare match“. The principle is, that the
internal compare signal (generated at a match between timer count and register contents) not only
manipulates the compare output but also sets the corresponding interrupt request flag. Thus, the
current task of the CPU is interrupted - of course provided the priority of the compare interrupt is
higher than the present task priority - and the corresponding interrupt service routine is called. This
service routine then sets up all the necessary parameters for the next compare event.
Advantages when using compare interrupts
Firstly, there is no danger of unintentional overwriting a compare register before a match has been
reached. This could happen when the CPU writes to the compare register without knowing about
the actual timer 2 count.
Secondly, and this is the most interesting advantage of the compare feature, the output pin is
exclusively controlled by hardware therefore completely independent from any service delay which
in real time applications could be disastrous. The compare interrupt in turn is not sensitive to such
delays since it loads the parameters for the next event. This in turn is supposed to happen after a
suff icient space of time.
Please note two special cases where a program using compare interrupts could show a “surprising“
behavior :
The first configuration has already been mentioned in the description of compare mode 1. The fact
that the compare interrupts are transition activated becomes important when driving timer 2 with a
slow external clock. In this case it should be carefully considered that the compare signal is active
as long as the timer 2 count is equal to the contents of the corresponding compare register, and that
the compare signal has a rising and a falling edge. Furthermore, the “shadow latches“ used in
compare mode 1 are transparent while the compare signal is active.
Thus, with a slow input clock for timer 2, the comparator signal is active for a long time (= high
number of machine cycles) and therefore a fast interrupt controlled reload of the compare register
could not only change the “shadow latch“ - as probably intended - but also the output buffer.
When using the CRC, you can select whether an interrupt should be generated when the compare
signal goes active or inactive, depending on the status of bit I3FR in T2CON.
Initializing the interrupt to be negative transition triggered is advisable in the above case. Then the
compare signal is already inactive and any write access to the port latch just changes the contents
of the “shadow-latch“.
Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal
goes active.
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