
S8S3122X16
CMOS SDRAM
Ver 0.0 Sep. '01
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-TCR2
-TCR1
Unit
Note
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
10
1000
10
1000
ns
1
CAS Latency=2
10
12
CLK to valid
output delay
CAS Latency=3
t
SAC
-
6
-
6
ns
1, 2
CAS Latency=2
-
6
-
8
Output data
t
OH
2.5
-
2.5
-
ns
2
CLK high pulse width
CAS Latency=3
t
CH
3
-
3.5
-
ns
3
CAS Latency=2
CLK low pulse width
CAS Latency=3
t
CL
3
-
3.5
-
ns
3
CAS Latency=2
Input setup time
CAS Latency=3
t
SS
2
-
2.5
-
ns
3
CAS Latency=2
Input hold time
t
SH
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
ns
2
CLK to output
in Hi-Z
CAS Latency=3
t
SHZ
-
6
-
6
ns
CAS Latency=2
-
6
-
8
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter
Symbol
version
Unit
-TCR2
10
20
20
20
48
-TCR1
10
20
20
20
48
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC
(
min
)
ns
ns
ns
ns
ns
us
ns
Row active time
100
Row cycle time
70
70