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參數(shù)資料
| 型號： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 945K |
| 代理商： | S25L004A0LMAI003 |
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March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
27
Ad va nc e
In forma t i o n
Figure 16. Release from Deep Power Down Instruction Sequence
Release from Deep Power Down and Read Electronic Signature (RES)
Once the device enters Deep Power Down mode, all instructions are ignored ex-
cept the RES instruction. The RES instruction can also be used to read the old-
style 8-bit Electronic Signature on the SO pin. The RES instruction always pro-
vides access to the Electronic Signature (except while an Erase, Program or
WRSR cycle is in progress), and can be applied even if DP mode is not entered.
Any RES instruction executed while an Erase, Program, or WRSR cycle is in
progress is not decoded, and has no effect on the cycle in progress.
The device features an 8-bit Electronic Signature, whose value for the S25FL004A
is 12h. This can be read using RES instruction.
The device is first selected by driving Chip Select (CS#) Low. The instruction code
is followed by three dummy bytes, each bit being latched-in on Serial Data Input
(SI) during the rising edge of Serial Clock (SCK). Then, the 8-bit Electronic Sig-
nature, stored in the memory, is shifted out on Serial Data Output (SO), each bit
being shifted out during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 17, on page 28.
The Release from Deep Power Down and Read Electronic Signature (RES) is ter-
minated by driving Chip Select (CS#) High after the Electronic Signature is read
at least once. Sending additional clock cycles on Serial Clock (SCK), while Chip
Select (CS#) is driven Low, causes the Electronic Signature to be output
repeatedly.
When Chip Select (CS#) is driven High, the device is placed in the Stand-by
Power mode. If the device was not previously in the Deep Power Down mode, the
transition to the Stand-by Power mode is immediate. If the device was previously
in the Deep Power Down mode, the transition to the Standby mode is delayed by
tRES, and Chip Select (CS#) must remain High for at lease tRES(max), as specified
in Table 10, on page 32. Once in the Stand-by Power mode, the device waits to
be selected, so that it can receive, decode, and execute instructions.
CS#
SCK
SI
0
1
23
4
5
6
7
Instruction
Deep Power Down Mode
tRES
Standby Mode
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