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參數(shù)資料
| 型號： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 5/39頁 |
| 文件大?。?/td> | 945K |
| 代理商： | S25L004A0LMAI003 |
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March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
11
Ad va nc e
In forma t i o n
Protection Modes
The SPI memory device boasts the following data protection mechanisms:
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its
reset state by the following events:
— Power-up
— Write Disable (WRDI) instruction completion
— Write Status Register (WRSR) instruction completion
— Page Program (PP) instruction completion
— Sector Erase (SE) instruction completion
— Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be con-
figured as read-only. This is the Software Protected Mode (SPM).
The Write Protect (W#) signal works in cooperation with the Status Register
Write Disable (SRWD) bit to enable write-protection. This is the Hardware
Protected Mode (HPM).
Program, Erase and Write Status Register instructions are checked to verify
that they consist of a number of clock pulses that is a multiple of eight, before
they are accepted for execution.
Table 2. Protected Area Sizes (S25FL004A).
Hold Condition Modes
The Hold (HOLD#) signal is used to pause any serial communications with the
device without resetting the clocking sequence. Hold (HOLD#) signal gates the
clock input to the device. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase Cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#)
Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal,
provided that this coincides with Serial Clock (SCK) being Low (as shown in
Protected
Memory
Area
(Top Level)
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0
Protected Area
Unprotected Area
0
none
00000-7FFFF
1/8
0
1
70000-7FFFF
00000-6FFFF
1/4
0
1
0
60000-7FFFF
00000-5FFFF
1/2
0
1
40000-7FFFF
00000-3FFFF
All
1
0
00000-7FFFF
none
All
1
0
1
00000-7FFFF
none
All
1
0
00000-7FFFF
none
All
1
00000-7FFFF
none
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