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參數(shù)資料
| 型號： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 945K |
| 代理商： | S25L004A0LMAI003 |
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March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
17
Ad va nc e
In forma t i o n
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be
read. The Status Register may be read at any time, even while a Program, Erase,
or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before
sending a new instruction to the device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 6.
Figure 6. Read Status Register (RDSR) Instruction Sequence
Figure 7. Status Register Format
The status and control bits of the Status Register are as follows:
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunc-
tion with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the Hard-
ware Protected mode (when the Status Register Write Disable (SRWD) bit is set
to 1, and Write Protect (W#) is driven Low). In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
BP2, BP1, BP0 bits: The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the area size to be software protected against Program and Erase in-
structions. These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 2, on page 11) becomes pro-
tected against Page Program (PP), and Sector Erase (SE) instructions. The Block
Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected
mode has not been set. The Bulk Erase (BE) instruction is executed if, and only
if, all Block Protect (BP2, BP1, BP0) bits are 0.
Instruction
High Impedance
MSB
Status Register Out
0
15
14
12
11
10
9
8
7
6
5
4
3
2
1
7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7
SO
SI
SCK
CS#
13
Status Register Write Disable
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
SRWD
0
BP1
BP0
WEL
WIP
b7
b0
BP2
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