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參數(shù)資料
| 型號(hào)： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 19/39頁 |
| 文件大小： | 945K |
| 代理商： | S25L004A0LMAI003 |
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24
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
Ad va n c e
In f o rm a t i o n
Figure 13. Sector Erase (SE) Instruction Sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets to 1 (FFh) all bits inside the entire memory.
Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction is decoded, the
device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, fol-
lowed by the instruction code, on Serial Data Input (SI). No address is required
for the Bulk Erase (BE) instruction. Chip Select (CS#) must be driven Low for the
entire sequence duration.
The instruction sequence is shown in Figure 14, on page 25.
Chip Select (CS#) must be driven High after the eighth bit of the last address byte
is latched in, otherwise the Bulk Erase (BE) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle
(whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle,
and is 0 when it is completed. At some unspecified time before the cycle is com-
pleted, the Write Enable Latch (WEL) bit is reset.
A Bulk Erase (BE) instruction is executed only if all the Block Protect (BP2, BP1,
BP0) bits (see Table 2, on page 11) are set to 0. The Bulk Erase (BE) instruction
is ignored if one or more sectors are protected.
CS#
SCK
SI
MSB
Instruction
24 Bit Address
01
2
3
4
5
6
7
8
9
10
28
29
30
31
23 22 21
3
2
1
0
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