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參數(shù)資料
| 型號： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 20/39頁 |
| 文件大?。?/td> | 945K |
| 代理商： | S25L004A0LMAI003 |
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March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
25
Ad va nc e
In forma t i o n
Figure 14. Bulk Erase (BE) Instruction Sequence
Deep Power Down (DP)
The Deep Power Down (DP) instruction puts the device in the lowest current
mode of 1 A typical.
It is recommended that the standard Standby mode be used for the lowest power
current draw, as well as the Deep Power Down (DP) as an extra software protec-
tion mechanism when this device is not in active use. In this mode, the device
ignores all Write, Program, and Erase instructions. Chip Select (CS#) must be
driven Low for the entire sequence duration.
The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#)
Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#)
must be driven Low for the entire sequence duration.
The instruction sequence is shown in Figure 15, on page 26.
Driving Chip Select (CS#) High after the eighth bit of the instruction code is
latched, places the device in Deep Power Down mode. The Deep Power Down
mode can only be entered by executing the Deep Power Down (DP) instruction to
As soon as Chip Select (CS#) is driven high, it requires a delay of tDP currently in
progress before Deep Power Down mode is entered.
Once the device enters the Deep Power Down mode, all instructions are ignored
except the Release from Deep Power Down (RES) and Read Electronic Signature.
This releases the device from the Deep Power Down mode. The Release from
Deep Power Down and Read Electronic Signature (RES) instruction also allows the
device’s Electronic Signature to be output on Serial Data Output (SO).
The Deep Power Down mode automatically stops at Power-down, and the device
always powers up in the Standby mode.
Any Deep Power Down (DP) instruction, while an Erase, Program, or WRSR cycle
is in progress, is rejected without having any effect on the cycle in progress.
01
2
4
5
6
7
Instruction
CS#
SCK
SI
3
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