參數(shù)資料
型號： S25L004A0LMAI003
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4M X 1 FLASH 3V PROM, PDSO8
封裝： 0.208 INCH, PLASTIC, SOP-8
文件頁數(shù)： 14/39頁
文件大?。?/td> 945K
代理商： S25L004A0LMAI003
March 28, 2005 S25FL004A_00_A1
S25FL Family (Serial Peripheral Interface) S25FL004A
19
Ad va nc e
In forma t i o n
Table 5. Protection Modes
Note: As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2, on page 11.
The device protection features are summarized in Table 5.
When the Status Register Write Disable (SRWD) bit is 0 (its initial delivery state),
it is possible to write to the Status Register provided that the Write Enable Latch
(WEL) bit has previously been set by a Write Enable (WREN) instruction, regard-
less of whether Write Protect (W#) is driven High or Low.
When the Status Register Write Disable (SRWD) bit is set to 1, two cases need to
be considered, depending on the state of Write Protect (W#):
If Write Protect (W#) is driven High, it is possible to write to the Status Reg-
ister provided that the Write Enable Latch (WEL) bit has previously been set
by a Write Enable (WREN) instruction.
If Write Protect (W#) is driven Low, it is not possible to write to the Status
Register even if the Write Enable Latch (WEL) bit has previously been set by
a Write Enable (WREN) instruction. (Attempts to write to the Status Register
are rejected, and are not accepted for execution). As a consequence, all the
data bytes in the memory area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Register, are also hardware pro-
tected against data modification.
Regardless of the two events order, the Hardware Protected Mode (HPM) can be
entered:
By setting the Status Register Write Disable (SRWD) bit after driving Write
Protect (W#) Low
or
By driving Write Protect (W#) Low after setting the Status Register Write Dis-
able (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull
Write Protect (W#) High.
If Write Protect (W#) is permanently tied High, the Hardware Protected Mode
(HPM) can never be activated, and only the Software Protected Mode (SPM),
using the Status Register’s Block Protect (BP2, BP1, BP0) bits, can be used.
Read Data Bytes (READ)
The READ instruction reads the memory at the specified SCK frequency (fSCK)
with a maximum speed of 33 MHz.
W# Signal SRWD Bit
Mode
Status Register Write
Protection
Protected Area
(See Note)
Unprotected Area
(See Note)
1
Software
Protected
(SPM)
Status Register is Writable (if the
WREN instruction sets the WEL bit)
The values in the SRWD, BP2, BP1
and BP0 bits can be changed
Protected against Page
Program and Erase
(SE, BE)
Ready to accept Page
Program and Sector
Erase Instructions
1
0
1
Hardware
Protected
(HPM)
Status Register is Hardware write
protected
The values in the SRWD, BP2, BP1
and BP0 bits cannot be changed
Protected against Page
Program and Erase
(SE, BE)
Ready to accept Page
Program and Sector
Erase Instructions
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