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參數(shù)資料
| 型號： | S25L004A0LMAI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 15/39頁 |
| 文件大?。?/td> | 945K |
| 代理商： | S25L004A0LMAI003 |
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
Ad va n c e
In f o rm a t i o n
The device is first selected by driving Chip Select (CS#) Low. The instruction code
for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-
A0), each bit being latched-in during the rising edge of Serial Clock (SCK). Then
the memory contents, at that address, are shifted out on Serial Data Output
(SO), each bit being shifted out, at a frequency fSCK, during the falling edge of
Serial Clock (SCK).
The instruction sequence is shown in Figure 9. The first byte addressed can be at
any location. The address automatically increments to the next higher address
after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction. When the highest address is
reached, the address counter rolls over to 00000h, allowing the read sequence to
be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output.
Any Read Data Bytes (READ) instruction, while a Program, Erase, or Write cycle
is in progress, is rejected without having any effect on the cycle that is in
progress.
Figure 9. Read Data Bytes (READ) Instruction Sequence
Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction reads the memory at the specified SCK frequency
(fSCK) with a maximum speed of 50 MHz. The device is first selected by driving
Chip Select (CS#) Low. The instruction code for (FAST_READ) instruction is fol-
lowed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-
in during the rising edge of Serial Clock (SCK). Then the memory contents, at that
address, are shifted out on Serial Data Output (SO), each bit being shifted out,
at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 10, on page 21. The first byte ad-
dressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single (FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to 00000h, allowing the read
sequence to be continued indefinitely.
Instruction
24-Bit Address
High Impedance
MSB
Data Out 1
Data Out 2
0
31 3 33 3 35 36 33 3
30
2
28
10
9
8
7
6
5
4
3
2
1
7 6 5
23 22 21
4
3 2 1 0
3 2 1 0 7
SO
SI
SCK
CS#
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