
Appendix D: Developing S1C17003 Mask ROM Code
AP-38
EPSON
S1C17003 TECHNICAL MANUAL
Appendix D: Developing S1C17003
Mask ROM Code
(1) Use the S1C17602 Flash microcomputer to develop mask ROM code for the S1C17003.
(2) The ROM data file format to submit to SEIKO EPSON should be “file.PAn” (output from winmdc). Before
submitting the file, perform final verification of the user ROM data using “file.psa” (output from sconv32).
(3) Specify the following values as the arguments for the S1C17003 when moto2ff is executed.
Data start address = 0x8000
Data block size
= 512
× 16 bits
(4) Take the differences listed in the table below into consideration and perform operation check using the
S1C17602.
Circuit/function
S1C17602
S1C17003
Memory
Boot address
0x8000
←
Flash
64KB
Mask ROM
64KB
IRAM
4KB
←
Display RAM
40B
Clock
Maximum operating frequency
8.2MHz
20MHz
IOSC oscillator circuit
Internal oscillator
OSC3 oscillator circuit
Crystal/Ceramic/External input
←
OSC1 oscillator circuit
Crystal/External input
←
Co-processor
Product-sum operation
16bit
×16bit+32bit(1cycle)
←
Divider
16bit 16bit(20cycle)
←
Peripheral
circuit
I/O port
36 (With Hi-z mode and input Schmitt
switching)
30 (Without Hi-z mode, and with fixed
Input Schmitt)
Input port
4 (Interface level AVDD)
SPI(master / slave)
1ch
←
I2C(master / slave)
1ch
←
UART(with IrDA1.0)
2ch
←
Infrared rays remote controller (REMC) 1ch
←
8-bit timer with the fine mode (T8F)
2ch
←
16-bit timer (T16)
3ch
←
PWM timer & Capture timer (T16E)
1ch
←
Clock timer(CT)
1ch
←
Stopwatch timer (SWT)
1ch
←
8-bit OSC1 timer (T8OSC1)
1ch
←
Watchdog timer (WDT)
1ch
←
LCD driver
36
×8 / 40×4
A/D converter
10bit
×8ch (±1.5LSB)
10bit
×4ch (±3LSB)
R/F converter
2ch
Power supply voltage detection (SVD)
circuit
1.8 to 3.2V detect
Power supply
Power supply voltage
VDD=1.8V to 3.6V (in normal
operation)
VDD=2.7V to 3.6V (while writing to
flash ROM)
(Regulator is built-in)
HVDD(I/O)=1.65V to 3.6V
LVDD(core)=1.65V to 1.95V
AVDD(Analog)=2.7V to 3.6V
Temperature
Operating temperatures
-20 to 70°C
-40 to 85°C
Configuration
Package
TQFP14-100
VFBGA7H-144
Bare chip 100 m pitch
TQFP12-64
WCSP 48pin
Bare chip 100 m pitch