
21 I2C Slave (I2CS)
21-14
EPSON
S1C17003 TECHNICAL MANUAL
0x4360: I2C Slave Transmit Data Register (I2CS_TRNS)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Transmit Data
Register
(I2CS_TRNS)
0x4360
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SDATA[7:0] I2C slave transmit data
0–0xff
0x0 R/W
D[15:8]
Reserved
D[7:0]
SDATA[7:0]: I2C Slave Transmit Data Bits
Set a transmit data in this register. (Default: 0x0)
The serial-converted data is output from the SDA1 pin beginning with the MSB, in which the bits set to
0 are output as low-level signals. When the data set in this register is sent to the shift register, a transmit
interrupt occurs. The next transmit data can be written to the register after that.
If the clock stretch function has been disabled, data must be written to this register within 7 cycles of
the I2C slave clock (SCL1) after a transmit interrupt has been occurred.
However, when setting the first transmit data after this module has been selected as the slave device,
follow the precautions described below.
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after
TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data
before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is
overwritten with the new data to be transferred. Therefore, the clear operation (see below) using
TBUF_CLR is unnecessary.
When the clock stretch function is enabled
The master device is placed into wait status by the clock stretch function, so transmit data can be
written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0],
it will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the
I2CS_TRNS register using TBUF_CLR (D8/I2CS_CTL register) before this module is selected as
the slave device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to
it.
It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before
TXEMP has been set.