
13 PWM Timer (T16E)
S1C17003 TECHNICAL MANUAL
EPSON
13-1
T16E
13 PWM Timer (T16E)
13.1 PWM Timer Overview
The S1C17003 incorporates a channel PWM Timer.
Figure 13.1.1 illustrates the PWM Timer configuration.
Compare data A register
T16E_CA
T16EDF[3:0]
PCLK-1/1 to 1/16K
Internal
data
bus
Prescaler clock selection
Compare A interrupt request
Compare B interrupt request
PWM output
ITo ITC
P36/TOUT3
P37/TOUTN3
P15/EXCL3
Compare data B register
T16E_CB
Compare A
signal
Up-counter
T16E_TC
Count
control
circuit
Output
control
circuit
Interrupt
control
circuit
Comparator
CLKSEL
Input clock selection
RUN/STOP control
T16ERUN
Clock output enable
OUTEN
Initial output level selection
INITOL
Inverted output
INVOUT
Fine mode selection
SELFM
Timer reset
T16ERST
Compare buffer enable
Compare A interrupt enable
CBUFEN
CAIE
Compare B interrupt enable
CBIE
Prescaler
Compare data A buffer
(T16E_CA)
Compare data B buffer
(T16E_CB)
Compare B
signal
Comparator
PWM timer
Figure 13.1.1: PWM Timer configuration
The PWM Timer includes a 16-bit up-counter (T16E_TC register), two 16-bit compare data registers (T16E_CA
and T16E_CB registers), and the corresponding buffers.
Software can configure the count value of the 16-bit counter, and reset it to 0, while an external signal from the
input/output port pin (EXCL3) or the Prescaler output clock counts up the 16-bit counter. Software can read the
count value.
The compare data A and B registers hold data for comparison against the up-counter contents. Data can be read
or written directly to or from the compare data registers. The compare data buffers enables loading to the compare
data registers of comparison values set when the counter is reset by software or by a compare B match signal.
Software can be used to set which of the compare data register and buffer the comparison values are written to.
If the counter value matches the contents of each compare data register, the comparator outputs a signal to control
interrupts and output signals. These registers can be used to program the interrupt occurrence cycle and output
clock frequency and duty ratio.