
25 Multiplier/Divider
25-2
EPSON
S1C17003 TECHNICAL MANUAL
25.2 Operating Mode and Output Mode
The multiplier/divider operates in accordance with the operating mode specified by the application program. The
multiplier/divider supports six different operations, as shown in Table 25.2.1.
The multiplication, division, and MAC arithmetic results are 32-bit data. This means the S1C17 core cannot read
out results in a single access cycle. The output mode is provided to specify whether the first 16 bits or last 16 bits
of the multiplier/divider arithmetic results are read out.
Specify the operating and output modes by writing 7-bit data to the multiplier/divider internal mode setting register.
Use the “l(fā)d.cw” instruction for writing.
ld.cw
%rd,%rs
%rs[6:0] is written to the mode setting register. (%rd: not used)
ld.cw
%rd,imm7
imm7
[6:0] is written to the mode setting register. (%rd: not used)
6
4
3
0
Output mode setting
Operating mode setting
Figure 25.2.1: Mode setting registers
Table 25.2.1: Mode setting
Setting
(D[6:4])
Output mode
Setting
(D[3:0])
Operating mode
0x0
Last 16-bit output mode
Last 16 bits of the arithmetic results are
read out as coprocessor output.
0x0
Initialization mode 0
Clears the arithmetic results register to 0x0.
0x1
First 16-bit output mode
First 16 bits of the arithmetic results are
read out as coprocessor output.
0x1
Initialization mode 1
Loads the 16-bit arithmetic augend into the
last 16 bits of the arithmetic results register.
0x2 to 0x7 Reserved
0x2
Initialization mode 2
Loads the 32-bit arithmetic augend into the
arithmetic results register.
0x3
Arithmetic results reading mode
Outputs the arithmetic results register data
without performing calculations.
0x4
Unsigned multiplication mode
Performs unsigned multiplication.
0x5
Signed multiplication mode
Performs signed multiplication.
0x6
Reserved
0x7
Signed MAC mode
Performs signed MAC multiplication.
0x8
Unsigned division mode
Performs unsigned division.
0x9
Signed division mode
Performs signed division.
0xa to 0xf Reserved