
10 Input/Output Port (P)
S1C17003 TECHNICAL MANUAL
EPSON
10-17
IOPort
0x5208/0x5218: Px Port Chattering Filter Control Register (Px_CHAT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port
Chattering
Filter Control
Register
(P0_CHAT)
0x5208
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P0CF2[2:0] P0[7:4] chattering filter time select
P0CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P0CF1[2:0] P0[3:0] chattering filter time select
P0CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P1 Port
Chattering
Filter Control
Register
(P1_CHAT)
0x5218
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P1CF2[2:0] P1[7:4] chattering filter time select
P0CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P1CF1[2:0] P1[3:0] chattering filter time select
P0CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
Note: The “x” in the bit names indicates the port number (0 or 1).
D7
Reserved
D[6:4]
PxCF2[2:0]: Px[7:4] Chattering Filter Time Select Bits
Set the chattering filter circuit included in the P0[7:4] or P1[7:4] ports.
D3
Reserved
D[2:0]
PxCF1[2:0]: Px[3:0] Chattering Filter Time Select Bits
Set the chattering filter circuit included in the P0[3:0] or P1[3:0]ports.
The P0 or P1 port includes a chattering filter circuit for key entry or port interrupt. You can select
whether to use this function respectively for P0[3:0], P0[7:4], P1[3:0] and P1[7:4] ports using
PxCF1/2[2:0]. You can also select relevant verification time accordingly.
Table 10.7.2: Chattering filter function settings
PxCF1[2:0], PxCF2[2:0]
Verification time *
0x7
16384/fPCLK (8ms)
0x6
8192/fPCLK (4ms)
0x5
4096/fPCLK (2ms)
0x4
2048/fPCLK (1ms)
0x3
1024/fPCLK (512s)
0x2
512/fPCLK (256s)
0x1
256/fPCLK (128s)
0x0
No verification time (Off)
(Default: 0x0, *when OSC3 = 2 MHz and PCLK = OSC3)