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| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 88/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
A-10
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
QSM
REFERENCE MANUAL
DTL = (system clock frequency
delay time) / 32
therefore,
DTL = ((16
10
6
) Hertz
(21.75
10
-6
) seconds) / 32
DTL = 10.88 which rounds up to 11
Plugging DTL = 11 into the original equation gives an actual delay of 22 ms.
A.6 QSPI Initialization and Operation
Since the fastest throughput is possible when using 10-bit transfers, the BITS field in
SPCR0 must be set to ten. Additionally, the BITSE bit must be set in each command
control byte associated with a transfer to the MC145050.
To simplify the example, assume conversions are only wanted from A/D channels 3,
4, and 6. Those channels will be sampled repeatedly, and each channel will have a
separate fixed memory address where the most recently acquired result will always be
available to the CPU. The WREN bit in SPCR2 and the first three queue entries will be
used. The transmit RAM must contain the A/D multiplexer address to be converted,
and the receive RAM will hold the conversion results.
Figure A-9
is an assembly language listing showing how the QSPI is configured to
perform the stated functions.The first portion of the program is definitions, followed by
initialization. The QSPI is then activated. The program waits until all conversions have
been performed once before utilizing the results.
Figure A-10
shows the setup and operation of the queue RAM in this example. It is
important to note that the conversion data requested by one queue entry is not shifted
out until the next transfer; thus, the data is stored in the receive RAM corresponding
to the latter transfer. Also, the very first transfer of output data from the A/D converter
is invalid and should be ignored. This issue can be handled by simply waiting a known
amount of time (until the first result has been updated).
Using a different approach, start the queue from entry F and then transfer and loop on
entries 0, 1, and 2. Queue entry F executes once; whereas, entries 0-2 will repeat in-
definitely, causing the invalid data word from the A/D converter to be stored in unused
RAM (associated with queue entry F). After SPIF in the SPSR is set, all A/D result lo-
cations will contain valid data. From then on, the CPU merely reads the latest A/D re-
sults from their fixed locations, effectively making the serial A/D converter appear to
the CPU as a parallel, memory-mapped peripheral. Having fixed locations for each
channel's result allows the programmer to equate them with sensor names, making
software easier to write and maintain (especially when compared to serial systems
funneling all results through a single receive register).
The example in
Figure A-9
shows an interrupt service routine which will generate a
warning if fuel pressure drops below a specific level. To cancel the warning, the pres-
sure must increase above a second threshold. Similarly, a heating element is con-
trolled to maintain an operator-specified temperature within a given range. Finally, an
F
Freescale Semiconductor, Inc.
n
.
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