參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 42/112頁(yè)
文件大?。?/td> 1496K
代理商： QSMRM
MOTOROLA
4-14
QSPI SUBMODULE
QSM
REFERENCE MANUAL
4.3.6.2 Transmit Data RAM
This segment of the RAM stores the data that is to be transmitted by the QSPI to pe-
ripherals. The CPU normally writes one word of data into this segment for each queue
command to be executed. If the corresponding peripheral, such as a serial input port,
is used solely to input data, then this segment does not need to be initialized.
Information to be transmitted by the QSPI should be written by the CPU to the transmit
data segment in a right-justified manner. The information in the transmit data segment
of the RAM cannot be modified by the QSPI. The QSPI merely copies the information
to its data serializer for transmission to a peripheral. Information in transmit RAM re-
mains there until it is re-written by the CPU.
4.3.6.3 Command RAM
The command segment of the QSPI RAM is used only by the QSPI when it is in master
mode. The CPU writes one byte of control information to this segment for each QSPI
command to be executed. The information in the command RAM cannot be modified
by the QSPI. It merely uses the information to perform the serial transfer.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The first, the
peripheral chip-select field, activates the correct serial peripheral during the transfer.
The second, the command control field, provides transfer options specifically for that
command/serial transfer. This feature gives the user more control over each transfer,
providing the flexibility to interface to external SPI chips with different requirements.
A maximum of 16 commands can be in the queue command control bytes. These
bytes are assigned an address from $0–$F. Queue execution by the QSPI proceeds
from the address contained in NEWQP through the address contained in ENDQP.
Both of these fields are contained in SPCR2.
*The PCS0 bit represents the dual-function PCS0/SS.
PCS[3:0]/SS — Peripheral Chip-Select
The four peripheral chip-select bits can be used directly to select one of four external
chips for the serial transfer, or decoded by external hardware to select one of 16 chip-
select patterns for the serial transfer. More than one peripheral chip-select may be ac-
tivated at a time, which is useful for broadcast messages in a multinode SPI system.
More than one peripheral chip may be connected to each PCS pin. Care must be taken
by the system designer not to exceed the maximum drive capability of the pins. See
the appropriate microcontroller user's manual for electrical specifications.
COMMAND RAM
— Command RAM
$YFFD40
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
$YFFD40
COMMAND CONTROL
PERIPHERAL CHIP-SELECT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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