參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 72/112頁(yè)
文件大?。?/td> 1496K
代理商： QSMRM
MOTOROLA
5-16
SCI SUBMODULE
QSM
REFERENCE MANUAL
5.4.1 Receiver Bit Processor
The receiver bit processor contains logic to synchronize the bit-time of the incoming
data and to evaluate the logic sense of each bit. To accomplish this an RT clock, which
is 16 times the baud rate, is used to sample each bit. Each bit-time can thus be divided
into 16 time periods called RT1–RT16. The receiver looks for a possible start bit by
watching for a high-to-low transition on the RXD pin and by assigning the RT time la-
bels appropriately.
When the receiver is enabled by writing RE in SCCR1 to one, the receiver bit proces-
sor logic begins an asynchronous search for a start bit. The goal of this search is to
gain synchronization with a frame. The bit-time synchronization is done at the begin-
ning of each frame so that small differences in the baud rate of the receiver and trans-
mitter are not cumulative. The SCI also synchronizes on all one-to-zero transitions in
the serial data stream, which makes the SCI tolerant to small frequency variations in
the received data stream.
The sequence of events used by the receiver to find a start bit is listed below.
A. Sample RXD input during each RT period and maintain these samples in a se-
rial pipeline that is three RT periods deep.
B. If RXD is low during this RT period, go to step A.
C. If RXD is high during this RT period, store sample and proceed to step D.
D. If RXD is low during this RT period, but not high for the previous three RT peri-
ods (which is noise only), set an internal working noise flag and go to step A,
since this transition was not a valid start bit transition.
E. If RXD is low during this RT period and has been high for the previous three RT
periods, call this period RT1, set RAF, and proceed to step F.
F. Skip RT2 but place RT3 in the pipeline and proceed to step G.
G. Skip RT4 and sample RT5. If both RT3 and RT5 are high (RT1 was noise only),
set an internal working noise flag. Go to step c and clear RAF. Otherwise, place
RT5 in the pipeline and proceed to step H.
H. Skip RT6 and sample RT7. If any two of RT3, RT5, or RT7 is high (RT1 was
noise only), set an internal working noise flag. Go to step c and clear RAF. Oth-
erwise, place RT7 in the pipeline and proceed to step I.
I.
A valid start bit is found and synchronization is achieved. From this point on until
the end of the frame, the RT clock will increment starting over again with RT1
on each one-to-zero transition or each RT16. The beginning of a bit-time is thus
defined as RT1 and the end of a bit-time as RT16.
Upon detection of a valid start bit, synchronization is established and is maintained
through the reception of the last stop bit, after which the procedure starts all over again
to search for a new valid start bit. During a frame's reception, the SCI resynchronizes
the RT clock on any one-to-zero transitions.
Additional logic in the receiver bit processor determines the logic level of the received
bit and implements an advanced noise-detection function. During each bit-time of a
frame (including the start and stop bits), three logic-sense samples are taken at RT8,
RT9, and RT10. The logic sense of the bit-time is decided by a majority vote of these
three samples. This logic level is shifted into register RDR for every bit except the start
and stop bits.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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