
MOTOROLA
4-6
QSPI SUBMODULE
QSM
REFERENCE MANUAL
CPHA determines which edge of SCK causes data to change and which edge of SCK
causes data to be captured. CPHA is used in conjunction with CPOL to produce the
desired clock-data relationship between master and slave device(s). Note that CPHA
is set at reset.
SPBR — Serial Clock Baud Rate
The QSPI internally generates the baud rate for SCK, the frequency of which is pro-
grammable by the user. The clock signal is derived from the MCU system clock using
a modulus counter. At reset, BAUD is initialized to a 2.1-MHz SCK frequency (16.78-
MHz system clock).
The user programs a baud rate for SCK by writing a baud value from 2 to 255. The
following equation determines the SCK baud rate:
SCK Baud Rate = System Clock/(2 *
SPBR)
(4-1)
or
SPBR = System Clock/(2 *
SCK Baud Rate Desired)
(4-2)
where SPBR equals 2, 3, 4,..., 255.
Programming SPBR with the values zero or one disables the QSPI baud rate genera-
tor. SCK is disabled and assumes its inactive state value. No serial transfers occur.
SPBR has 254 active values.
Table 4-3
lists several possible baud values and the cor-
responding SCK frequency based on a 16.78-MHz system clock.
4.3.2 QSPI Control Register 1 (SPCR1)
SPCR1 contains parameters for configuring the QSPI before it is enabled. Although
the CPU can read and write this register, the QSM has read access only, except for
SPE. This bit is automatically cleared by the QSPI after completing all serial transfers
or when a mode fault occurs.
Table 4-3 Examples of SCK Frequencies
System Clock
Frequency
16.78 MHz
Required
Division Ratio
4
8
16
34
168
510
Value of
SPBR
2
4
8
17
84
255
Actual
SCK Frequency
4.19 MHz
2.10 MHz
1.05 MHz
493 kHz
100 kHz
33 kHz
SPCR1
— QSPI Control Register 1
$YFFC1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPE
DSCKL
DTL
RESET:
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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