參數(shù)資料
型號： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊串行模塊參考手冊
文件頁數(shù)： 35/112頁
文件大小： 1496K
代理商： QSMRM
QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-7
SPE — QSPI Enable
1 = The QSPI is enabled and the pins allocated by QSM register PQSPAR are con-
trolled by the QSPI.
0 = The QSPI is disabled, and the seven QSPI pins can be used as general-pur-
pose I/O pins, regardless of the values in PQSPAR.
This bit enables or disables the QSPI submodule. Setting SPE causes the QSPI to be-
gin operation. If the QSPI is a master, setting SPE causes the QSPI to begin initiating
serial transfers. If the QSPI is a slave, the QSPI begins monitoring the PCS0/SS pin
to respond to the external initiation of a serial transfer.
When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is en-
abled, both the QSPI and the CPU have access to the QSPI RAM. The CPU has both
read and write access capability to all 80 bytes of the QSPI RAM. The QSPI can read
only the transmit data segment and the command control segment, and can write only
the receive data segment of the QSPI RAM.
The QSPI turns itself off automatically when it is finished by clearing SPE. An error
condition called mode fault (MODF) also clears SPE. This error occurs when PCS0/
SS is configured for input, the QSPI is a system master (MSTR = 1), and PCS0/SS is
driven low externally.
To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR
is set. SPE may then be safely cleared to zero, providing an orderly method of quickly
shutting down the QSPI after the current serial transfer is completed. The CPU can
immediately disable the QSPI by just clearing SPE; however, loss of data from a cur-
rent serial transfer may result and confuse an external SPI device.
DSCKL — Delay before SCK
This bit determines the length of time the QSPI delays from peripheral chip-select
(PCS) valid to SCK transition for serial transfers in which the command control bit,
DSCK of the QSPI RAM, equals one. PCS may be any of the four peripheral chip-se-
lect pins. The following equation determines the actual delay before SCK:
PCS to SCK Delay = [DSCKL/System Clock Frequency]
(4-3)
where DSCKL equals {1,2,3,... 127}.
NOTE
A zero value for DSCKL causes a delay of 128/system clocks, which
equals 7.6 μs for a 16.78-MHz system clock. Because of design lim-
its, a DSCKL value of one defaults to the same timing as a value of
two.
If a queue entry's DSCK equals zero, then DSCKL is not used. Instead, the PCS valid-
to-SCK transition is one-half SCK period.
DTL — Length of Delay after Transfer
These bits determine the length of time that the QSPI delays after each serial transfer
in which the command control bit, DT of the QSPI RAM, equals one. The following
equation is used to calculate the delay:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
QSOP-24 Package MQA24
QST4 Low frequency amplifier
QST9 General purpose amplification (−30V, −1A)
QSX7 General purpose amplification (12V, 1.5A)
QSZ1 General purpose transistor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
QSMS-0136 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE, PART NUMBER ASSIGNED TO REPLACE HSMS-0005 - Gel-pak, waffle pack, wafer, diced wafer on film
QSMS-2926-TR1G 制造商:Avago Technologies 功能描述:SCHOTTKY DIODE - Tape and Reel
QSMT-AW13-NSUZ1 制造商:Avago Technologies 功能描述:MS AV,1W CWHITE - Tape and Reel
QSMT-FW85-NX000 制造商:Avago Technologies 功能描述:THIS HIGH BRIGHTNESS LED LIGHT SOURCE
QSMT-L060-227NG 制造商:Avago Technologies 功能描述:L2 LED CONTOUR LIGHTING,COLORLESS - Rail/Tube
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*