參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 43/112頁(yè)
文件大?。?/td> 1496K
代理商： QSMRM
QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-15
QSM register PORTQS determines the state of the PCS pins when the QSPI is dis-
abled, and also determines the state of PCS pins that are not assigned to the QSPI
when the QSPI is enabled. PORTQS determines the state of pins assigned to the
QSPI between transfers as well.
To use a peripheral chip-select pin, the CPU assigns the pin to the QSPI in PQSPAR
by writing a one to the appropriate bit. The default value of the PCS pin should be writ-
ten to PORTQS. Next, the pin must be defined as an output in DDRQS by setting the
appropriate bit, which causes the pin to start driving the default value.
The QSPI RAM may then be initialized for a serial transmission, with the peripheral
chip-select bits of the command control byte appropriately configured to activate the
desired PCS pin(s) during the serial transfer. When the command is executed, the
PCS pin(s) are driven to the values contained in the appropriate control byte. After
completing the serial transfer, the QSPI returns control of the peripheral chip-select
signal(s) (if CONT = 0 in the command control byte) to register PORTQS.
CONT — Continue
1 = Keep peripheral chip-selects asserted after transfer is complete
0 = Return control of peripheral chip-selects to PORTQS after transfer is complete
Some peripheral chips must be deselected between every QSPI transfer. Other chips
must remain selected between several sequential serial transfers. CONT is designed
to provide the flexibility needed to handle both cases.
If CONT = 1 and the peripheral chip-select pattern for the next command is the same
as that of the present command, the QSPI drives the PCS pins to the same value con-
tinuously during the two serial transfers. An unlimited number of serial transfers may
be sent to the same peripheral(s) without deselecting it (them) by setting CONT = 1.
If CONT = 1 and the peripheral chip-select pattern for the next command is different
from that of the present command, the QSPI drives the PCS pins to the new value for
the second serial transfer. Although this case is similar to CONT = 0, a difference re-
mains. When CONT = 1, the QSPI continues to drive the PCS pins using the pattern
from the first transfer until it switches to using the pattern for the second transfer.
When CONT = 0, the QSPI drives the PCS pins to the values found in register
PORTQS between serial transfers.
BITSE — Bits Per Transfer Enable
1 = Number of bits set in BITS field of SPCR0
0 = Eight bits
DT — Delay After Transfer
A/D converters require a known amount of time to perform a conversion. The conver-
sion time for serial CMOS A/D converters may range from 1 – 100 μs.
To facilitate interfacing to peripherals with a latency requirement, the QSPI provides a
programmable delay at the end of the serial transfer, with the DT field. The user may
avoid using this delay option by executing transfers with other peripheral devices in be-
tween transfers with the peripheral that requires a delay. This interleaved operation im-
proves the effective serial transfer rate.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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