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| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁數(shù)： | 41/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-13
RAM by the CPU are coherent accesses because these accesses are an indivisible
operation. If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot
access the QSPI RAM until the CPU is finished. However, a long-word or misaligned
word access is not coherent because the CPU must break its access of the QSPI RAM
into two parts, which allows the QSPI to access the QSPI RAM between the two ac-
cesses by the CPU.
The RAM is divided into three segments: receive data RAM, transmit data RAM, and
command control RAM. Receive data is information received from a serial device ex-
ternal to the MCU. Transmit data is information stored by the CPU for transmission to
an external peripheral chip. Command control contains all the information needed by
the QSPI to perform the transfer.
Figure 4-2
illustrates the organization of the RAM.
Figure 4-2 Organization of the QSPI RAM
Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the
QSPI operates independently of the CPU. The QSPI executes all of the commands in
its queue, sets a flag indicating that it is finished, and then either interrupts the CPU or
waits for CPU intervention.
4.3.6.1 Receive Data RAM
This segment of the RAM stores the data that is received by the QSPI from peripher-
als, SPI bus masters, or other MCUs. The CPU reads this segment of RAM to retrieve
the data from the QSPI. Data stored in receive RAM is right-justified, i.e., the least sig-
nificant bit is always in the right-most bit position within the word (bit 0) regardless of
the serial transfer length. Unused bits in a receive queue entry are set to zero by the
QSPI upon completion of the individual queue entry. The CPU can access the data
using byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
RECEIVE
RAM
TRANSMIT
RAM
D00
D1E
D20
D3E
WORD
D40
D4F
COMMAND
RAM
BYTE
WORD
RR0
RR1
RR2
RRD
RRE
RRF
TR0
TR1
TR2
TRD
TRE
TRF
CR0
CR1
CR2
CRD
CRE
CRF
0
F
ENTRY
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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