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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 66/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
5-10
SCI SUBMODULE
QSM
REFERENCE MANUAL
NOTE
None of the status bits are cleared by reading a status bit while it is
asserted and then by writing zero to that same bit. The procedure
outlined above must be followed. Emphasis is also given to note that
reading either byte of register SCSR causes all 16 bits to be access-
ed, and any status bits already set in either byte are armed to clear
on a subsequent read or write of register SCDR.
As mentioned, register SCSR co-functions with register SCDR. SCDR is a combina-
tion of two data registers: the TDR and the RDR. Each of these data registers has a
serial shifter.
Bits [15:9] — Not Implemented
TDRE — Transmit Data Register Empty Flag
1 = A new character may now be written to register TDR
0 = Register TDR still contains data to be sent to the transmit serial shifter
TDRE is set when the byte in register TDR is transferred to the transmit serial shifter.
If this bit is zero, the transfer is yet to occur and a write to TDR will overwrite the pre-
vious value. New data is not transmitted if TDR is written without first clearing TDRE,
which is accomplished by reading register SCSR with TDRE set, followed by a write
to TDR. Reset sets this bit.
TC — Transmit Complete Flag
1 = SCI transmitter is idle
0 = SCI transmitter is busy
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/
idle line), or queued breaks (logic zero). TC is cleared when SCSR is read with TC set,
followed by a write to register TDR.
RDRF — Receive Data Register Full Flag
1 = Register RDR contains new data
0 = Register RDR is empty or contains previously read data
RDRF is set when the content of the receive serial shifter is transferred to register
RDR. If one or more errors are detected in the received word, the appropriate receive-
related flag(s) NF, FE, and/or PF are set within the same clock cycle. RDRF is cleared
when register SCSR is read with RDRF set, followed by a read of register RDR.
SCSR
— SCI Status Register
$YFFC0C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
RESET:
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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