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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊 |
| 文件頁數(shù)： | 26/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
3-10
CONFIGURATION AND CONTROL
QSM
REFERENCE MANUAL
3.3.2 QSM Pin Assignment Register (PQSPAR)
PQSPAR determines which of the QSPI pins, with the exception of the SCK pin, are
actually used by the QSPI submodule, and which pins are available for general-pur-
pose I/O. Pins may be assigned to the QSPI or to function as general-purpose I/O on
a pin-by-pin basis. QSPI pins designated by PQSPAR as general-purpose I/O are con-
trolled only by DDRQS and PORTQS and the QSPI has no effect on these pins. PQS-
PAR does not affect the operation of the SCI submodule.
Bit 15 — Not Implemented
TE in register SCCR1 determines whether the TXD pin is controlled by the SCI or func-
tions as a general-purpose I/O pin.
PCS[3:1] — Peripheral Chip-Selects 3–1
PCS0/SS — Peripheral Chip-Select 0/Slave Select
These bits determine whether the associated QSM port pins function as general-pur-
pose I/O pins or are assigned to the QSPI submodule.
Bit 10 — Not Implemented
(When the QSPI is enabled, the SCK pin is required.)
MOSI — Master Out Slave In
MISO — Master In Slave Out
These bits determine whether the associated QSM port pin functions as a general-pur-
pose I/O pin or is assigned to the QSPI submodule.
3.3.3 QSM Data Direction Register (DDRQS)
DDRQS sets each I/O pin, except for TXD, as an input or an output regardless of
whether the QSPI submodule is enabled or disabled. All QSM pins are configured dur-
ing reset as general-purpose inputs. (The QSPI and SCI are disabled.) The RXD pin
remains an input pin dedicated to the SCI submodule and does not function as a gen-
eral-purpose I/O pin.
PORTQS
— QSM Port Data Register
$YFFC15
15
8
7
6
5
4
3
2
1
0
RESERVED
DATA7
(TXD)
DATA6
(PCS3)
DATA5
(PCS2)
DATA4
(PCS1)
DATA3
(PCS0/SS)
DATA2
(SCK)
DATA1
(MOSI)
DATA0
(MISO)
RESET:
0
0
0
0
0
0
0
0
PQSPAR
— QSM Pin Assignment Register
$YFFC16
15
14
13
12
11
10
9
8
7
0
0
PCS3
PCS2
PCS1
PCSO/SS
0
MOSI
MISO
DDRQS*
RESET:
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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