參數(shù)資料
型號： PSD4235G2-A-20UI
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 40/104頁
文件大小： 1114K
代理商： PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
Memory blocks delailed operation
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The
Flash memory then returns to reading array data mode.
7.1.8
Erasing Flash memory
Flash Bulk Erase
The Flash Bulk Erase instruction uses six write operations followed by a Read operation of
the status register, as described in Table 22. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6,
and DQ7 (DQ13, DQ14, DQ15), as detailed in Section 7.1.6: Programming Flash memory.
The Error bit (returns a ‘1’ if there has been an Erase Failure (maximum number of erase
cycles have been executed).
It is not necessary to program the array with 00h because the PSD4135G2/G2V will
automatically do this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory will not accept any
instructions.
Flash Sector Erase
The Sector Erase instruction uses six write operations, as described in Table 22. Additional
Flash Sector Erase confirm commands and Flash sector addresses can be written
subsequently to erase other Flash sectors in parallel, without further coded cycles, if the
additional instruction is transmitted in a shorter time than the timeout period of about 100 s.
The input of a new Sector Erase instruction will restart the timeout period.
The status of the internal timer can be monitored through the level of DQ3 (DQ11) (Erase
timeout bit). If DQ3 (DQ11) is ‘0’, the Sector Erase instruction has been received and the
timeout is counting. If DQ3 (DQ11) is ‘1’, the timeout has expired and the PSD4135G2/G2V
is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other
than Erase suspend and Erase Resume will abort the instruction and reset the device to
Read Array mode. It is not necessary to program the Flash sector with 00h as the
PSD4135G2/G2V will do this automatically before erasing.
During a Sector Erase, the memory status may be checked by reading status bits DQ5,
DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in Section 7.1.6: Programming Flash
During execution of the erase instruction, the Flash block logic accepts only Reset and
Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to
read data from another Flash sector, and then resumed.
Suspend Sector Erase
When a Sector Erase operation is in progress, the Erase Suspend instruction will suspend
the operation by writing 0B0h to any even address when an appropriate Chip Select (FSi or
CSBOOTi) is true. (See Table 22). This allows reading of data from another Flash sector
after the Erase operation has been suspended. Erase suspend is accepted only during the
Flash Sector Erase instruction execution and defaults to read array mode. An Erase
Suspend instruction executed during an Erase timeout will, in addition to suspending the
erase, terminate the time out.
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