參數(shù)資料
型號(hào)： PSD4235G2-A-20UI
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 35/104頁(yè)
文件大?。?/td> 1114K
代理商： PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
Memory blocks delailed operation
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
Error flag DQ5 (DQ14 for Motorola)
During a normal Program or Erase cycle, the Error bit will set to ‘0’. This bit is set to ‘1’ when
there is a failure during Flash programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a word.
In case of an error in Flash sector erase or word program, the Flash sector in which the error
occurred or to which the programmed location belongs must no longer be used. Other Flash
sectors may still be used. The Error bit resets after the Reset instruction. A reset instruction
is required after detecting the error bit.
Erase Timeout flag DQ3 (DQ11 for Motorola)
The Erase Timer bit reflects the timeout period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time
period of 100 s + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3
(DQ11) is set to ‘1’. A reset instruction is required after detecting the erase timer bit.
7.1.6
Programming Flash memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Flash memory sector erases to all logic ones, and its bits
are programmed to logic zeros. Although erasing Flash memory occurs on a sector or chip
basis, programming Flash memory occurs on a word basis.
The PSD4135G2/G2V primary Flash and secondary Flash memories require the MCU to
send an instruction to program a word or perform an erase function (see Table 22).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the
PSD4135G2/G2V support several means to provide status to the MCU. Status may be
checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output
pin.
Data polling
Polling on DQ7 (DQ15) is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD4135G2/G2V begins. The MCU then reads the location of the word to be programmed
in Flash to check status. Data bit DQ7 (DQ15) of this location becomes the compliment of
data bit 7of the original data word to be programmed. The MCU continues to poll this
location, comparing DQ7 (DQ15) and monitoring the Error bit on DQ5 (DQ13). When the
DQ7 (DQ15) matches data bit 7 of the original data, and the Error bit at DQ5 (DQ13)
remains ‘0’, then the embedded algorithm is complete. If the Error bit at DQ5 is ‘1’, the MCU
should test DQ7 (DQ15) again since DQ7 (DQ15) may have changed simultaneously with
DQ5 (DQ13) (see Figure 6).
The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the
embedded algorithm attempted to program the location or if the MCU attempted to program
a ‘1’ to a bit that was not erased (not erased is logic ‘0’).
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