參數(shù)資料
型號(hào): PSD4235G2-A-20UI
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁(yè)數(shù): 25/104頁(yè)
文件大?。?/td> 1114K
代理商: PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
Register bit definition
Doc ID 7838 Rev 2
PLD Array CLK:
0: CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD
when Turbo bit is off.
1: CLKIN to the PLD AND array is disconnected, saving power.
6.11
PMMR2 register
For bit 4, bit 3, bit 2: See Table 27 for the signals that are blocked on pins CNTL0-CNTL2.
PLD Array Addr:
0: Address A7-A0 are connected to the PLD array.
1 Address A7-A0 are blocked from the PLD array, saving power.
Note:
In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4).
PLD Array CNTL2:
0: CNTL2 input to the PLD AND array is connected.
1: CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1
0: CNTL1 input to the PLD AND array is connected.
1: CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0
0: CNTL0 input to the PLD AND array is connected.
1: CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE
0: ALE input to the PLD AND array is connected.
1: ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH
0: WRH/DBE input to the PLD AND array is connected.
1: WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 17.
PMMR2 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
PLD
Array
WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to ’0’)
PLD
Array Addr
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