- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299790 > PSD4235G2-A-20UI (STMICROELECTRONICS) 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD4235G2-A-20UI |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 30/104頁 |
| 文件大?。?/td> | 1114K |
| 代理商： | PSD4235G2-A-20UI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
Memory blocks delailed operation
Doc ID 7838 Rev 2
7.1.1
Memory Block Selects signals
The decode PLD in the PSD4135G2/G2V generates the chip selects for all the internal
memory blocks (refer to Section 8: PLDs). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four
secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up
to three product terms. Having three product terms for each sector select signal allows a
given sector to be mapped in different areas of system memory. When using a
microcontroller (80C51XA) with separate Program and Data space, these flexible select
signals allow dynamic re-mapping of sectors from one space to the other before and after
IAP.
7.1.2
Ready/Busy pin (PE4)
Pin PE4 can be used to output the Ready/Busy status of the PSD4135G2/G2V. The output
on the pin will be a ‘0’ (Busy) when Flash memory blocks are being written to,
or when the
Flash memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase
operation is in progress.
7.1.3
Memory Operation
The primary Flash and secondary Flash memories are addressed through the
microcontroller interface on the PSD4135G2G2V devices. The microcontroller can access
these memories in one of two ways:
●
The microcontroller can execute a typical bus write or read
operation just as it would if
accessing a RAM or ROM device using standard bus cycles.
●
The microcontroller can execute a specific
instruction that consists of several write and
read operations. This involves writing specific data patterns to special addresses within
the Flash to invoke an embedded algorithm. These instructions are summarized in
Typically, Flash memory can be read by the microcontroller using read operations, just as it
would read a ROM device. However, Flash memory can only be erased and programmed
with specific instructions. For example, the microcontroller cannot write a single word
directly to Flash memory as one would write a word to RAM. To program a word into Flash
memory, the microcontroller must execute a program instruction sequence, then test the
status of the programming event. This status test is achieved by a read operation or polling
the Rdy/Busy pin (PE4).
The Flash memory can also be read by using special instructions to retrieve particular Flash
device information (sector protect status and ID).
Instructions
An instruction is defined as a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard write operation. The
instruction is executed when the correct number of bytes are properly received and the time
between two consecutive bytes is shorter than the time-out value. Some instructions are
structured to include read operations after the initial write operations.
The sequencing of any instruction must be followed exactly. Any invalid combination of
instruction bytes or time-out between two consecutive bytes while addressing Flash memory
will reset the device logic into a read array mode (Flash memory reads like a ROM device).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813F2A-15JI | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD834F2VA-15MI | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| PSD854F2A-90MT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| PSD854F2A-90UT | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| PSH665-FREQ-OUT1 | VCXO, SINE OUTPUT, 465 MHz - 865 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。