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參數(shù)資料
| 型號： | PSD4235G2-A-20UI |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 32/104頁 |
| 文件大小： | 1114K |
| 代理商： | PSD4235G2-A-20UI |
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Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
Memory blocks delailed operation
Doc ID 7838 Rev 2
Unlock Bypass
1
AAh@
XAAAh
55h@
X554h
20h@
XAAAh
Unlock Bypass
Program(13)
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset(14)
1
90h@
XXXXh
00h@
XXXXh
1.
All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2.
All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses, RA = Address of the memory
location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR,
CNTL0). PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to
be erased, or verified, must be Active (High).
3.
Only address bits A11-A0 are used in instruction decoding.
4.
All WRITE bus cycles in an instruction are byte WRITE to an even address (XA4Ah or X554h). A Flash memory Program
bus cycle writes a word to an even address.
5.
Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express.
6.
No Unlock or instruction cycles are required when the device is in the READ mode.
7.
The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector
Protection Status, or if the Error Flag bit (DQ5/DQ13) goes high.
8.
The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
and (A1,A0)=(1,0)
9.
The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the
instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the
Sector Protection Status of the primary Flash memory.
10. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector
Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a
Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock
Bypass mode.
Table 22.
Instructions(1)(2)(3) (continued)
Instruction(4)
FS0-FS7 or
CSBOOT0-
CSBOOT3(5)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
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