參數(shù)資料
型號(hào)： PSD4235G2-A-20UI
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 19/104頁(yè)
文件大?。?/td> 1114K
代理商： PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
PSD architectural overview
Doc ID 7838 Rev 2
3.6
In-system programming (ISP)
Using the JTAG signals on Port E, the entire PSD4135G2/G2V (memory, logic,
configuration) devices can be programmed or erased without the use of the microcontroller.
3.7
In-application programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller
executing the programming algorithms out of the secondary Flash memory, or SRAM. Since
this is a sizable separate block, the application can also continue to operate. The secondary
Flash boot memory can be programmed the same way by executing out of the main Flash
memory. Table 5 indicates which programming methods can program different functional
blocks of the PSD4135G2/G2V.
3.8
Page register
The eight-bit Page Register expands the address range of the microcontroller by up to 256
times.The paged address can be used as part of the address space to access external
memory and peripherals or internal memory and I/O. The Page Register can also be used to
change the address mapping of blocks of Flash memory into different memory spaces for
IAP.
3.9
Power management unit (PMU)
The power management unit (PMU) in the PSD4135G2/G2V gives the user control of the
power consumption on selected functional blocks based on system requirements. The PMU
includes an automatic power-down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power-down mode that helps reduce power
consumption.
The PSD4135G2 and PSD4135G2V also have some bits that are configured at run-time by
the MCU to reduce power consumption of the GPLD. The turbo bit in the PMMR0 register
can be turned off and the GPLD will latch its outputs and go to standby until the next
transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the GPLD to reduce power consumption (see Section 11: Power management).
Table 5.
Methods of programming different functional blocks of the PSD
Functional block
JTAG-ISP
Device
programmer
IAP
Primary Flash memory
Yes
Secondary Flash memory
Yes
PLD Array (DPLD and GPLD)
Yes
No
PSD configuration
Yes
No
相關(guān)PDF資料
PDF描述
PSD813F2A-15JI 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD834F2VA-15MI 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90MT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PSD854F2A-90UT 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
PSH665-FREQ-OUT1 VCXO, SINE OUTPUT, 465 MHz - 865 MHz
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4256G6V-10UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4-36 制造商:Tamura Corporation of America 功能描述:
PSD-45 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply
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