參數(shù)資料
型號： PSD4235G2-A-20UI
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 21/104頁
文件大?。?/td> 1114K
代理商： PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
PSD register description and address offsets
Doc ID 7838 Rev 2
5
PSD register description and address offsets
Table 6 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers. Table 6 provides brief descriptions of the registers in CSIOP space.
The following sections give a more detailed description.
Table 6.
Register address offset
Register name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Other(1)
Description
Data In
00
01
10
11
30
40
41
Reads Port pin as input, MCU I/O
input mode
Control
32
42
43
Selects mode between MCU I/O or
Address Out
Data Out
04
05
14
15
34
44
45
Stores data for output to Port pins,
MCU I/O output mode
Direction
06
07
16
17
36
46
47
Configures Port pin as input or output
Drive Select
08
09
18
19
38
48
49
Configures Port pins as either CMOS
or Open Drain on some pins, while
selecting high slew rate on other pins.
Flash Memory
Protection
C0
Read only - Primary Flash Sector
Protection
Flash Boot
Protection
C2
Read only - PSD Security and
secondary Flash memory Sector
Protection
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
Page
E0
Page register
VM
E2
Places PSD memory areas in
Program and/or Data space on an
individual basis.
Memory_ID0
F0
Read only - SRAM and Primary
memory size
Memory_ID1
F1
Read only - Secondary memory type
and size
1.
Other registers that are not part of the I/O ports.
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