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參數(shù)資料
| 型號： | PSD4235G2-A-20UI |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 34/104頁 |
| 文件大?。?/td> | 1114K |
| 代理商： | PSD4235G2-A-20UI |
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Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
Memory blocks delailed operation
Doc ID 7838 Rev 2
Data Polling flag DQ7 (DQ15 for Motorola)
When Erasing or Programming the Flash memory bit DQ7 (DQ15) outputs the complement
of the bit being entered for Programming/Writing on DQ7 (DQ15). Once the Program
instruction or the Write operation is completed, the true logic value is read on DQ7 (DQ15)
(in a Read operation). Flash memory specific features:
●
Data Polling is effective after the fourth Write pulse (for programming) or after the sixth
Write pulse (for Erase). It must be performed at the address being programmed or at an
address within the Flash sector being erased.
●
During an Erase instruction, DQ7 (DQ15) outputs a ‘0’. After completion of the
instruction, DQ7 (DQ15) will output the last bit programmed (it is a ‘1’ after erasing).
●
If the location to be programmed is in a protected Flash sector, the instruction is
ignored.
●
If all the Flash sectors to be erased are protected, DQ7 (DQ15) will be set to ‘0’ for
about 100 s, and then return to the previous addressed location. No erasure will be
performed.
Toggle flag DQ6 (DQ14 for Motorola)
The PSD4135G2 and PSD4135G2V offer another way for determining when the Flash
memory Program instruction is completed. During the internal Write operation and when
either the FSi or CSBOOTi is true, the DQ6 (DQ14) will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on
subsequent attempts to read any word of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the Data Bus
is the addressed memory location. The device is now accessible for a new Read or Write
operation. The operation is finished when two successive reads yield the same output data.
Flash memory specific features:
●
The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase).
●
If the location to be programmed belongs to a protected Flash sector, the instruction is
ignored.
●
If all the Flash sectors selected for erasure are protected, DQ6 (DQ14) will toggle to ‘0’
for about 100 s and then return to the previous addressed location.
Table 23.
Status bits
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Data
Polling
Toggle
Flag
Error Flag
X
Erase
timeout
XX
X
Table 24.
Status bits for Motorola(1)(2)(3)
1.
X = Not guaranteed value, can be read either 1 or 0.
2.
DQ15-DQ0 represent the Data Bus bits, D15-D0.
3.
FS0-FS7/CSBOOT0-CSBOOT3 are active high.
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Data
Polling
Toggle
Flag
Error Flag
X
Erase
timeout
XX
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
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