參數(shù)資料
型號： PSD4235G2-A-20UI
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 16/104頁
文件大?。?/td> 1114K
代理商： PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
PSD4135G2, PSD4135G2V
PSD architectural overview
Doc ID 7838 Rev 2
3
PSD architectural overview
PSD4135G2 and PSD4135G2V devices contain several major functional blocks. Figure 4:
Detailed block diagram shows the architecture of the device family. The functions of each
block are described briefly in the following sections. Many of the blocks perform multiple
functions and are user configurable.
3.1
Memory
The devices contain the following memories:
●
4 Mbit Flash
●
A secondary 256 Kbit Flash memory for boot or data
●
64 Kbit SRAM.
The 4 Mbit Flash is the main memory of the PSD4135G2/G2V. It is divided into eight
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each
sector is individually selectable.
The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
3.2
PLDs
The device contains two PLD blocks, each optimized for a different function, as shown in
Table 3. The functional partitioning of the PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD4135G2/G2V internal memory and registers. The general purpose PLD (GPLD) can
implement user-defined external chip selects and logic functions. The PLDs receive their
inputs from the PLD input bus and are differentiated by their output destinations, number of
Product Terms.
The PLDs consume minimal power by using zero-power design techniques. The speed and
power consumption of the PLD is controlled by the Turbo bit in the PMMR0 register and
other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime.
There is a slight penalty to PLD propagation time when invoking the non-Turbo bit.
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