參數(shù)資料
型號(hào): PSD4235G2-A-20UI
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 4M X 1 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁(yè)數(shù): 33/104頁(yè)
文件大?。?/td> 1114K
代理商: PSD4235G2-A-20UI
Obsolete
Product(s)
- Obsolete
Product(s)
Memory blocks delailed operation
PSD4135G2, PSD4135G2V
Doc ID 7838 Rev 2
7.1.4
Power-up condition
The PSD4135G2/G2V internal logic is reset upon power-up to the read array mode. The FSi
and CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
data being written on the first edge of a write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
7.1.5
Reading Flash memory
Under typical conditions, the microcontroller may read the Flash, or secondary Flash
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read special
data from these memories. The following sections describe these read functions.
Reading Memory content
Primary Flash and secondary Flash memories are placed in the read array mode after
power-up, chip reset, or a Reset Flash instruction (see Table 22). The microcontroller can
read the memory contents of primary Flash or secondary Flash by using read operations
any time the read operation is not part of an instruction.
Reading Primary Flash Identifier
The primary Flash identifier is read with an instruction composed of 4 operations: 3 specific
write operations and a read operation (see Table 22). The PSD4135G2/G2V primary Flash
memory ID is E8h. The secondary Flash does not support this instruction.
Reading Memory Sector Protection status
The Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 22). The read
operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (primary Flash or secondary Flash) can also
be read by the microcontroller accessing the Flash Protection and Flash Boot Protection
registers in PSD I/O space. See Section 6.7: Flash Memory Protection register and
Reading the Erase/Program Status bits
The PSD4135G2 and PSD4135G2V provide several status bits to be used by the
microcontroller to confirm the completion of an erase or programming instruction of Flash
memory. These status bits minimize the time that the microcontroller spends performing
these tasks and are defined in Table 23. The status byte resides in even location and can be
read as many times as needed. Please note DQ15-8 is even byte for Motorola MCUs with
16 bit data bus.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
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PSD813F2A-15JI 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
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