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參數(shù)資料
| 型號： | PNX8526 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable source decoder with integrated peripherals |
| 中文描述： | 可編程集成外設(shè)源解碼器 |
| 文件頁數(shù)： | 6/59頁 |
| 文件大?。?/td> | 3319K |
| 代理商： | PNX8526 |
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Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
6 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
C/BE[1]
C/BE[0]
CLK
DEVSEL
AE8
AD10
AA1
AF7
I/O
I/O
I
I/O
Multiplexed Command or Byte Enable 1
Multiplexed Command or Byte Enable 0
PCI Bus Clock
Device Select is asserted when a target address is decoded and remains
asserted to indicate that a target device is selected.
Frame is asserted to indicate start of bus transaction and remains
asserted until final data phase begins.
Arbitration Grant is asserted to indicate access to the bus has been
granted. This pin is an input when an external arbiter is used and an
output when using the internal arbiter.
Auxiliary Arbitration Grant_A is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is
configured.
Auxiliary Arbitration Grant_B
is asserted to indicate bus access has been
granted to an external PCI master. Used where internal arbiter is
configured.
Initialization Device Select provides chip select during configuration read
and write transactions.
Interrupt A is asserted to request an interrupt. This pin may be configured
as an input if the internal PIC is used, or as an output if the external
interrupt controller is used. Polarity in active low.
Initiator Ready is asserted during writes to indicate valid data on
AD[31:0]. Also asserted during reads to indicate the target is prepared to
accept data. Wait states are inserted until IRDY and TRDY are both
asserted.
Parity supports even parity across the PCI Address/Data Bus AD[31:0])
and Command/ Byte Enable Bus (C/BE[3:0]). The Bus Master drives PAR
for address and write data phases. The Target drives PAR for the read
data phases.
Parity Error indicates data parity errors during all PCI transactions except
Special Cycle.
Arbitration Request on PCI Bus. Request is an output when using an
external arbiter and an input when using an internal arbiter.
Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal
arbiter is configured.
Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal
arbiter is configured.
PCI Bus Global Reset
System Error
Stop is asserted to indicate a request from the target for the master to
stop the current transmission.
Target Ready is asserted during reads to indicate valid data on AD[31:0].
It is asserted during writes to indicate the target is prepared to accept
data. Wait states are inserted until IRDY and TRDY are both asserted.
FRAME
AF6
I/O
GNT
Y3
I/O
GNT_A
Y4
I/O
#
GNT_B
AA4
I/O
#
IDSEL
AF3
I/O
INTA
V4
I/O
IRDY
AE6
I/O
PAR
AF8
I/O
PERR
AD7
I/O
REQ
Y2
I/O
REQ_A
AA2
I/O
#
REQ_B
AA3
I/O
#
RESET_IN
SERR
STOP
W3
AC7
AE7
I
I/O
I/O
TRDY
AD6
I/O
Table 3:
# indicates multiplexed signal, see
Section 6.2.1
for more details.
Symbol
Pin
Type
Peripheral Controller Interface (PCI)
…continued
Description
Alternate
Function
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