參數(shù)資料
型號(hào): PNX8526
廠商: NXP Semiconductors N.V.
英文描述: Programmable source decoder with integrated peripherals
中文描述: 可編程集成外設(shè)源解碼器
文件頁數(shù): 50/59頁
文件大小: 3319K
代理商: PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
50 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
DV_CLK period is programmable via the internal PLL
13.12 Digital Video Input (DV Input) timing
13.13 Transport Stream Output (TSO) timing
Fig 17. DV Input timing
Table 35:
Symbol
t
su
t
h
f
DVB
DV Input timing (VDICLK-referenced)
Parameter
[7:0] setup
[7:0] hold
Clock
Min
3
3
-
Typical
-
-
27
Max
-
-
-
Unit
ns
ns
MHz
handbook, 4 columns
CLOCK
1.5 V
1.5 V
1.5 V
INPUTS
(DATA, SOP,
ERROR, VALID)
MCE555
fDVB
tsu
th
Fig 18. TSO timing
Table 36:
Symbol
t
su
t
h
TSO timing
Parameter
Data setup
Data hold
Min
3
0
Typical
-
-
Max
-
-
Unit
ns
ns
handbook, 4 columns
CLOCK
OUTPUT
(DATA, SOP,
VALID)
MCE556
tsu
th
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