參數(shù)資料
型號： PNX8526
廠商： NXP Semiconductors N.V.
英文描述： Programmable source decoder with integrated peripherals
中文描述： 可編程集成外設源解碼器
文件頁數(shù)： 25/59頁
文件大小： 3319K
代理商： PNX8526
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
25 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC1_DA
DV_OUT2[3]
DV_OUT2[1]
DV_OUT2[0]
SSI_RXD
V
DDC1
V
DDC1
DV3_ERR
UA1_TX
UA1_RX
UA2_RX
SSI_SCLK_CTSN
SSI_FS_RTSN
SSI_TXD
INTA
V
DDC1
V
DDC1
DV3_DATA[2]
T26
U1
U2
U3
U4
U5
U22
U23
U24
U25
U26
V1
V2
V3
V4
V5
V22
V23
COM
AVIF
AVIF
AVIF
COM
PWR
PWR
DVB
COM
COM
COM
COM
COM
COM
PCI
PWR
PWR
DVB
I/O
O
O
O
I/O
-
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
Smart Card1 Data
Digital Video Output2, Bit 3 for secondary display channel from AICP
Digital Video Output2, Bit 1 for secondary display channel from AICP
Digital Video Output2, Bit 0 for secondary display channel from AICP
Synchronous Serial Interface Receive
System 1.26 Volts
System 1.26 Volts
Digital Video Transport Stream3 Error
UART1 Transmit
UART1 Receive
UART2 Receive
Synchronous Serial Interface CLock
Synchronous Serial Interface Frame Sync
Synchronous Serial Interface Transmit
Interrupt Acknowledge is asserted to request an interrupt.
System 1.26 Volts
System 1.26 Volts
Digital Video Transport Stream3 Data Bit 2
DV3_SOP
DV3_VALID
DV3_CLK
USB_PWR
V24
V25
V26
W1
DVB
DVB
DVB
USB
I
I
I
O
Digital Video Transport Stream3 Start of Packet
Digital Video Transport Stream3 Data Valid
Digital Video Transport Stream3 Clock
USB port power On/Off
0 = Power on
1 = Power off
Indicates over current being drawn by a USB device:
0 = Over current detected
1 = No over current
PCI Bus Global Reset
General Purpose PLL Clock Output
System 3.3 Volts
System 3.3 Volts
Digital Video Transport Stream3 Data Bit 7
Digital Video Transport Stream3 Data Bit 3
Digital Video Transport Stream3 Data Bit 1
Digital Video Transport Stream3 Data Bit 0
System Reset Output
Arbitration Request on PCI Bus. Request is an output when using an
external arbiter and an input when using an internal arbiter.
Arbitration Grant is asserted to indicate access to the bus has been
granted. This pin is an input when an external arbiter is used and an
output when using the internal arbiter.
USB_OVRCUR
W2
USB
I
RESET_IN
PLL_OUT
V
DD1
V
DD1
DV3_DATA[7]
DV3_DATA[3]
DV3_DATA[1]
DV3_DATA[0]
SYS_RSTN_OUT
REQ
W3
W4
W5
W22
W23
W24
W25
W26
Y1
Y2
PCI
PLL
PWR
PWR
DVB
DVB
DVB
DVB
MISC
PCI
I
O
-
-
I
I
I
I
O
I/O
GNT
Y3
PCI
I/O
Table 16:
Symbol
All pins
…continued
Pin
Group
Type
Description
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